专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20110103128A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110103128A1
公开(公告)日：2011-05-05
申请号：US12882685
申请日：2010-09-15
申请人： Hiroshi Kanno , Reika Ichihara , Takayuki Tsukamoto , Kenichi Murooka , Hirofumi Inoue
发明人： Hiroshi Kanno , Reika Ichihara , Takayuki Tsukamoto , Kenichi Murooka , Hirofumi Inoue
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C7/02 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0064 , G11C13/0097 , G11C2213/31 , G11C2213/71 , G11C2213/72
摘要： Nonvolatile semiconductor memory device of an embodiment includes: a memory cell array including a plurality of first and second lines intersecting each other and plural memory cells provided at intersections of the first and second lines and having data written and erased upon application of voltages of the same polarity; and a writing circuit configured to select first and second lines and supply a set or reset pulse to the memory cell through the selected first and second lines. In an erase operation, the writing circuit repeatedly supplies the reset pulse to a selected memory cell until data is erased, by increasing or decreasing voltage level and voltage application time of the reset pulse within a reset region. The reset region, or an aggregate of combinations of voltage level and voltage application time of the reset pulse, is a region where voltage level and voltage application time are negatively correlated.
摘要翻译：一个实施例的非易失性半导体存储器件包括：存储单元阵列，包括彼此相交的多个第一和第二线，以及设置在第一和第二线的交点处的多个存储单元，并且在施加相同的电压时写入和擦除数据极性; 以及写入电路，被配置为选择第一和第二行，并且通过所选择的第一和第二行向存储器单元提供置位或复位脉冲。在擦除操作中，写入电路通过增加或减小复位区域内的复位脉冲的电压电平和电压施加时间，将复位脉冲重复地提供给所选择的存储单元，直到数据被擦除。复位区域或复位脉冲的电压电平和电压施加时间的组合的总和是电压电平和电压施加时间呈负相关的区域。

2. 发明授权

US08320158B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08320158B2
公开(公告)日：2012-11-27
申请号：US12882685
申请日：2010-09-15
申请人： Hiroshi Kanno , Reika Ichihara , Takayuki Tsukamoto , Kenichi Murooka , Hirofumi Inoue
发明人： Hiroshi Kanno , Reika Ichihara , Takayuki Tsukamoto , Kenichi Murooka , Hirofumi Inoue
IPC分类号： G11C11/00
CPC分类号： G11C7/02 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0064 , G11C13/0097 , G11C2213/31 , G11C2213/71 , G11C2213/72
摘要： Nonvolatile semiconductor memory device of an embodiment includes: a memory cell array including a plurality of first and second lines intersecting each other and plural memory cells provided at intersections of the first and second lines and having data written and erased upon application of voltages of the same polarity; and a writing circuit configured to select first and second lines and supply a set or reset pulse to the memory cell through the selected first and second lines. In an erase operation, the writing circuit repeatedly supplies the reset pulse to a selected memory cell until data is erased, by increasing or decreasing voltage level and voltage application time of the reset pulse within a reset region. The reset region, or an aggregate of combinations of voltage level and voltage application time of the reset pulse, is a region where voltage level and voltage application time are negatively correlated.
摘要翻译：一个实施例的非易失性半导体存储器件包括：存储单元阵列，包括彼此相交的多个第一和第二线，以及设置在第一和第二线的交点处的多个存储单元，并且在施加相同的电压时写入和擦除数据极性; 以及写入电路，被配置为选择第一和第二行，并且通过所选择的第一和第二行向存储器单元提供置位或复位脉冲。在擦除操作中，写入电路通过增加或减小复位区域内的复位脉冲的电压电平和电压施加时间，将复位脉冲重复地提供给所选择的存储单元，直到数据被擦除。复位区域或复位脉冲的电压电平和电压施加时间的组合的总和是电压电平和电压施加时间呈负相关的区域。

3. 发明授权

US08391048B2 Non-volatile semiconductor memory device including memory cells with a variable resistor 有权
标题翻译：包括具有可变电阻器的存储单元的非易失性半导体存储器件
公开(公告)号：US08391048B2
公开(公告)日：2013-03-05
申请号：US12846198
申请日：2010-07-29
申请人： Reika Ichihara , Takayuki Tsukamoto , Kenichi Murooka , Hirofumi Inoue , Hiroshi Kanno
发明人： Reika Ichihara , Takayuki Tsukamoto , Kenichi Murooka , Hirofumi Inoue , Hiroshi Kanno
IPC分类号： G11C11/00
CPC分类号： G11C13/0061 , G11C13/0007 , G11C13/0023 , G11C13/0069 , G11C13/0097 , G11C2013/0092
摘要： A non-volatile semiconductor memory device according to an aspect of embodiments of the present invention includes a memory cell array including: multiple first wirings; multiple second wirings crossing the multiple first wirings; and multiple electrically rewritable memory cells respectively arranged at intersections of the first wirings and the second wirings, and each formed of a variable resistor which stores a resistance value as data in a non-volatile manner. The non-volatile semiconductor memory device according to an aspect of the embodiments of the present invention further includes a controller for selecting a given one of the memory cells, generating an erase pulse which is used for erasing data, and supplying the erase pulse to the selected memory cell. The erase pulse has a pulse width which is increased or decreased exponentially in accordance with an access path length to the selected memory cell.
摘要翻译：根据本发明的实施例的非易失性半导体存储器件包括：存储单元阵列，包括：多个第一布线; 多个第二布线穿过多个第一布线; 以及分别布置在第一布线和第二布线的交点处的多个电可重写存储器单元，并且每个由可变电阻器形成，其以非易失性方式存储电阻值作为数据。根据本发明的实施例的一个方面的非易失性半导体存储器件还包括一个控制器，用于选择给定的一个存储单元，产生用于擦除数据的擦除脉冲，并将擦除脉冲提供给选择的存储单元。擦除脉冲具有根据到所选存储单元的访问路径长度指数地增加或减少的脉冲宽度。

4. 发明申请

US20110032745A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110032745A1
公开(公告)日：2011-02-10
申请号：US12846198
申请日：2010-07-29
申请人： Reika ICHIHARA , Takayuki Tsukamoto , Kenichi Murooka , Hirofumi Inoue , Hiroshi Kanno
发明人： Reika ICHIHARA , Takayuki Tsukamoto , Kenichi Murooka , Hirofumi Inoue , Hiroshi Kanno
IPC分类号： G11C11/00
CPC分类号： G11C13/0061 , G11C13/0007 , G11C13/0023 , G11C13/0069 , G11C13/0097 , G11C2013/0092
摘要： A non-volatile semiconductor memory device according to an aspect of embodiments of the present invention includes a memory cell array including: multiple first wirings; multiple second wirings crossing the multiple first wirings; and multiple electrically rewritable memory cells respectively arranged at intersections of the first wirings and the second wirings, and each formed of a variable resistor which stores a resistance value as data in a non-volatile manner. The non-volatile semiconductor memory device according to an aspect of the embodiments of the present invention further includes a controller for selecting a given one of the memory cells, generating an erase pulse which is used for erasing data, and supplying the erase pulse to the selected memory cell. The erase pulse has a pulse width which is increased or decreased exponentially in accordance with an access path length to the selected memory cell.
摘要翻译：根据本发明的实施例的非易失性半导体存储器件包括：存储单元阵列，包括：多个第一布线; 多个第二布线穿过多个第一布线; 以及分别布置在第一布线和第二布线的交点处的多个电可重写存储器单元，并且每个由可变电阻器形成，其以非易失性方式存储电阻值作为数据。根据本发明实施例的一个方面的非易失性半导体存储器件还包括用于选择给定的一个存储单元的控制器，产生用于擦除数据的擦除脉冲，并将擦除脉冲提供给选择的存储单元。擦除脉冲具有根据到所选存储单元的访问路径长度指数地增加或减少的脉冲宽度。

5. 发明申请

US20120012807A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20120012807A1
公开(公告)日：2012-01-19
申请号：US13182095
申请日：2011-07-13
申请人： Takeshi YAMAGUCHI , Hirofumi Inoue , Reika Ichihara , Takayuki Tsukamoto , Takashi Shigeoka , Katsuyuki Sekine , Shinya Aoki
发明人： Takeshi YAMAGUCHI , Hirofumi Inoue , Reika Ichihara , Takayuki Tsukamoto , Takashi Shigeoka , Katsuyuki Sekine , Shinya Aoki
IPC分类号： H01L45/00
CPC分类号： H01L45/146 , H01L27/2409 , H01L45/08 , H01L45/1233
摘要： A semiconductor memory device in an embodiment comprises memory cells, each of the memory cells disposed between a first line and a second line and having a variable resistance element and a switching element connected in series. The variable resistance element includes a variable resistance layer configured to change in resistance value thereof between a low-resistance state and a high-resistance state. The variable resistance layer is configured by a transition metal oxide. A ratio of transition metal and oxygen configuring the transition metal oxide varies between 1:1 and 1:2 along a first direction directed from the first line to the second line.
摘要翻译：实施例中的半导体存储器件包括存储单元，每个存储单元设置在第一线和第二线之间，并且具有串联连接的可变电阻元件和开关元件。可变电阻元件包括可变电阻层，其被配置为在低电阻状态和高电阻状态之间改变其电阻值。可变电阻层由过渡金属氧化物构成。构成过渡金属氧化物的过渡金属和氧的比例沿着从第一线指向第二线的第一方向在1:1和1:2之间变化。

6. 发明授权

US08759806B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08759806B2
公开(公告)日：2014-06-24
申请号：US13182095
申请日：2011-07-13
申请人： Takeshi Yamaguchi , Hirofumi Inoue , Reika Ichihara , Takayuki Tsukamoto , Takashi Shigeoka , Katsuyuki Sekine , Shinya Aoki
发明人： Takeshi Yamaguchi , Hirofumi Inoue , Reika Ichihara , Takayuki Tsukamoto , Takashi Shigeoka , Katsuyuki Sekine , Shinya Aoki
IPC分类号： H01L29/02
CPC分类号： H01L45/146 , H01L27/2409 , H01L45/08 , H01L45/1233
摘要： A semiconductor memory device in an embodiment comprises memory cells, each of the memory cells disposed between a first line and a second line and having a variable resistance element and a switching element connected in series. The variable resistance element includes a variable resistance layer configured to change in resistance value thereof between a low-resistance state and a high-resistance state. The variable resistance layer is configured by a transition metal oxide. A ratio of transition metal and oxygen configuring the transition metal oxide varies between 1:1 and 1:2 along a first direction directed from the first line to the second line.
摘要翻译：实施例中的半导体存储器件包括存储单元，每个存储单元设置在第一线和第二线之间，并且具有串联连接的可变电阻元件和开关元件。可变电阻元件包括可变电阻层，其被配置为在低电阻状态和高电阻状态之间改变其电阻值。可变电阻层由过渡金属氧化物构成。构成过渡金属氧化物的过渡金属和氧的比例沿着从第一线指向第二线的第一方向在1:1和1:2之间变化。

7. 发明申请

US20110122676A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110122676A1
公开(公告)日：2011-05-26
申请号：US12887043
申请日：2010-09-21
申请人： Kenichi MUROOKA , Hirofumi Inoue
发明人： Kenichi MUROOKA , Hirofumi Inoue
IPC分类号： G11C11/00
CPC分类号： G11C5/063 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/003 , G11C2213/35 , G11C2213/71 , G11C2213/75 , H01L27/2436 , H01L27/2454 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/149
摘要： According to one embodiment, a semiconductor memory device includes: word lines; bit lines; an insulating film; an interlayer insulating film; and a resistance varying material. The word lines, the bit lines and the insulating film configure a field-effect transistor at each of the intersections of the word lines and the bit lines. The field-effect transistor has one of the word lines as a control electrode and one of the bit lines as a channel region. The field-effect transistor and the resistance varying material configure a memory cell having the field-effect transistor and the resistance varying material connected in parallel. Each of the bit lines includes a first surface opposing the word lines, and a second surface on an opposite side to the first surface. The resistance varying material is disposed in contact with the second surface and has a portion thereof in contact with the interlayer insulating film.
摘要翻译：根据一个实施例，半导体存储器件包括：字线; 位线绝缘膜; 层间绝缘膜; 和电阻变化材料。字线，位线和绝缘膜在字线和位线的每个交点处构成场效应晶体管。场效应晶体管具有作为控制电极的字线之一和位线之一作为沟道区。场效应晶体管和电阻变化材料配置具有并联连接的场效应晶体管和电阻变化材料的存储单元。每个位线包括与字线相对的第一表面和与第一表面相反的一侧上的第二表面。电阻变化材料设置成与第二表面接触并且其一部分与层间绝缘膜接触。

8. 发明授权

US08254160B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08254160B2
公开(公告)日：2012-08-28
申请号：US12887043
申请日：2010-09-21
申请人： Kenichi Murooka , Hirofumi Inoue
发明人： Kenichi Murooka , Hirofumi Inoue
IPC分类号： G11C11/00
CPC分类号： G11C5/063 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/003 , G11C2213/35 , G11C2213/71 , G11C2213/75 , H01L27/2436 , H01L27/2454 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/149
摘要： According to one embodiment, a semiconductor memory device includes: word lines; bit lines; an insulating film; an interlayer insulating film; and a resistance varying material. The word lines, the bit lines and the insulating film configure a field-effect transistor at each of the intersections of the word lines and the bit lines. The field-effect transistor has one of the word lines as a control electrode and one of the bit lines as a channel region. The field-effect transistor and the resistance varying material configure a memory cell having the field-effect transistor and the resistance varying material connected in parallel. Each of the bit lines includes a first surface opposing the word lines, and a second surface on an opposite side to the first surface. The resistance varying material is disposed in contact with the second surface and has a portion thereof in contact with the interlayer insulating film.
摘要翻译：根据一个实施例，半导体存储器件包括：字线; 位线绝缘膜; 层间绝缘膜; 和电阻变化材料。字线，位线和绝缘膜在字线和位线的每个交点处构成场效应晶体管。场效应晶体管具有作为控制电极的字线之一和位线之一作为沟道区。场效应晶体管和电阻变化材料配置具有并联连接的场效应晶体管和电阻变化材料的存储单元。每个位线包括与字线相对的第一表面和与第一表面相反的一侧上的第二表面。电阻变化材料设置成与第二表面接触并且其一部分与层间绝缘膜接触。

9. 发明授权

US08625248B2 Electrostatic discharge protector 失效
标题翻译：静电放电保护器
公开(公告)号：US08625248B2
公开(公告)日：2014-01-07
申请号：US13123262
申请日：2009-10-06
申请人： Mina Onishi , Yoshimitsu Ishihara , Hirofumi Inoue , Yukihiko Azuma
发明人： Mina Onishi , Yoshimitsu Ishihara , Hirofumi Inoue , Yukihiko Azuma
IPC分类号： H02H1/04 , H02H3/22
CPC分类号： H01C7/12 , H01T4/10 , H05K1/0259 , H05K2201/09672 , H05K2201/09881
摘要： The present invention provides an electrostatic discharge protector capable of protecting electronic circuit boards having various designs from electrostatic discharge freely, simply and easily. The electrostatic discharge protector of the present invention comprises at least three conductive members containing one pair of electrodes and the conductive members other than the electrodes, the conductive members are each disposed in such a way that the gap between one conductive member and the other conductive member has a width of 0.1 to 10 μm, an insulating member is disposed and embedded in at least one of gaps having a width of 0.1 to 10 μm which are adjacent to each conductive member and one electrode is connected to the other electrode paired with the one electrode through the insulating member and the conductive members other than electrodes.
摘要翻译：本发明提供一种静电放电保护器，其能够简单且容易地保护具有各种设计的电子电路板免受静电放电。本发明的静电放电保护器包括至少三个包含一对电极的导电构件和除电极之外的导电构件，导电构件各自设置成使得一个导电构件和另一个导电构件之间的间隙具有0.1至10微米的宽度，绝缘构件设置并嵌入在与每个导电构件相邻的宽度为0.1至10μm的间隙中的至少一个中，并且一个电极连接到与该一个配对的另一个电极电极通过绝缘构件和除电极之外的导电构件。

10. 发明授权

US08398091B2 Suspension system for vehicle 有权
标题翻译：车辆悬挂系统
公开(公告)号：US08398091B2
公开(公告)日：2013-03-19
申请号：US12935703
申请日：2009-05-08
申请人： Hirofumi Inoue , Takuhiro Kondo
发明人： Hirofumi Inoue , Takuhiro Kondo
IPC分类号： B60G17/0165
CPC分类号： B60G17/0157 , B60G17/06 , B60G2202/42 , B60G2400/102 , B60G2400/206 , B60G2400/252
摘要： A suspension system for a vehicle, including: an electromagnetic actuator configured to generate an actuator force and including a sprung-side unit supported by a sprung portion, an unsprung-side unit supported by an unsprung portion, a screw mechanism, and an electromagnetic motor; a connecting mechanism including a support spring for permitting one of the sprung-side and unsprung-side units to be floatingly supported as a floating unit by a unit-floatingly support portion that is one of the sprung and unsprung portions by which the floating unit is supported; and a controller including a sprung-vibration-damping control portion and a relative-vibration-damping control portion that is configured to execute a relative-vibration damping control for damping a vibration of the floating unit caused by the structure in which the floating unit is floatingly supported by the support spring.
摘要翻译：一种用于车辆的悬架系统，包括：电磁致动器，其被配置为产生致动器力，并且包括由簧上部支撑的簧上侧单元，由簧下部支撑的簧下侧单元，螺旋机构和电磁马达 ; 一种连接机构，包括：支撑弹簧，用于通过单元浮动支撑部分将所述簧上侧和簧下侧单元中的一个作为浮动单元浮动地支撑，所述单元浮动支撑部分是所述浮动单元和簧下侧单元之一支持的; 以及控制器，其包括弹簧减振控制部分和相对减振控制部分，所述相关减振控制部分被配置为执行相对振动衰减控制，以减缓由所述浮动单元是由支撑弹簧浮动支撑。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式