会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 2. 发明授权
    • Nonvolatile semiconductor memory device
    • 非易失性半导体存储器件
    • US08320158B2
    • 2012-11-27
    • US12882685
    • 2010-09-15
    • Hiroshi KannoReika IchiharaTakayuki TsukamotoKenichi MurookaHirofumi Inoue
    • Hiroshi KannoReika IchiharaTakayuki TsukamotoKenichi MurookaHirofumi Inoue
    • G11C11/00
    • G11C7/02G11C13/0004G11C13/0007G11C13/0011G11C13/0064G11C13/0097G11C2213/31G11C2213/71G11C2213/72
    • Nonvolatile semiconductor memory device of an embodiment includes: a memory cell array including a plurality of first and second lines intersecting each other and plural memory cells provided at intersections of the first and second lines and having data written and erased upon application of voltages of the same polarity; and a writing circuit configured to select first and second lines and supply a set or reset pulse to the memory cell through the selected first and second lines. In an erase operation, the writing circuit repeatedly supplies the reset pulse to a selected memory cell until data is erased, by increasing or decreasing voltage level and voltage application time of the reset pulse within a reset region. The reset region, or an aggregate of combinations of voltage level and voltage application time of the reset pulse, is a region where voltage level and voltage application time are negatively correlated.
    • 一个实施例的非易失性半导体存储器件包括:存储单元阵列,包括彼此相交的多个第一和第二线,以及设置在第一和第二线的交点处的多个存储单元,并且在施加相同的电压时写入和擦除数据 极性; 以及写入电路,被配置为选择第一和第二行,并且通过所选择的第一和第二行向存储器单元提供置位或复位脉冲。 在擦除操作中,写入电路通过增加或减小复位区域内的复位脉冲的电压电平和电压施加时间,将复位脉冲重复地提供给所选择的存储单元,直到数据被擦除。 复位区域或复位脉冲的电压电平和电压施加时间的组合的总和是电压电平和电压施加时间呈负相关的区域。
    • 4. 发明申请
    • NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
    • 非易失性半导体存储器件
    • US20110032745A1
    • 2011-02-10
    • US12846198
    • 2010-07-29
    • Reika ICHIHARATakayuki TsukamotoKenichi MurookaHirofumi InoueHiroshi Kanno
    • Reika ICHIHARATakayuki TsukamotoKenichi MurookaHirofumi InoueHiroshi Kanno
    • G11C11/00
    • G11C13/0061G11C13/0007G11C13/0023G11C13/0069G11C13/0097G11C2013/0092
    • A non-volatile semiconductor memory device according to an aspect of embodiments of the present invention includes a memory cell array including: multiple first wirings; multiple second wirings crossing the multiple first wirings; and multiple electrically rewritable memory cells respectively arranged at intersections of the first wirings and the second wirings, and each formed of a variable resistor which stores a resistance value as data in a non-volatile manner. The non-volatile semiconductor memory device according to an aspect of the embodiments of the present invention further includes a controller for selecting a given one of the memory cells, generating an erase pulse which is used for erasing data, and supplying the erase pulse to the selected memory cell. The erase pulse has a pulse width which is increased or decreased exponentially in accordance with an access path length to the selected memory cell.
    • 根据本发明的实施例的非易失性半导体存储器件包括:存储单元阵列,包括:多个第一布线; 多个第二布线穿过多个第一布线; 以及分别布置在第一布线和第二布线的交点处的多个电可重写存储器单元,并且每个由可变电阻器形成,其以非易失性方式存储电阻值作为数据。 根据本发明实施例的一个方面的非易失性半导体存储器件还包括用于选择给定的一个存储单元的控制器,产生用于擦除数据的擦除脉冲,并将擦除脉冲提供给 选择的存储单元。 擦除脉冲具有根据到所选存储单元的访问路径长度指数地增加或减少的脉冲宽度。
    • 5. 发明授权
    • Nonvolatile semiconductor memory device
    • 非易失性半导体存储器件
    • US08320157B2
    • 2012-11-27
    • US12876637
    • 2010-09-07
    • Reika IchiharaTakayuki TsukamotoHiroshi KannoKenichi Murooka
    • Reika IchiharaTakayuki TsukamotoHiroshi KannoKenichi Murooka
    • G11C11/00
    • G11C13/0069G11C13/0007G11C13/0097G11C2213/13G11C2213/34G11C2213/72
    • According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of first wirings, a plurality of second wirings intersecting the plurality of first wirings, and a plurality of memory cells provided at the intersections of the plurality of first and second wirings and each including a non-ohmic element and a variable resistance element connected in series. The control circuit selects one of the plurality of memory cells, generates an erasing pulse for erasing data from the selected memory cell, and supplies the erasing pulse to the selected memory cell. The control circuit executes data erase by applying a voltage of the erasing pulse to the non-ohmic element in the reverse bias direction.
    • 根据一个实施例,非易失性半导体存储器件包括存储单元阵列和控制电路。 存储单元阵列包括多个第一布线,与多条第一布线相交的多条第二布线,以及多个存储单元,设置在多个第一布线和第二布线的交点处,每个包括非欧姆元件和 串联连接的可变电阻元件。 控制电路选择多个存储单元中的一个,产生用于从所选存储单元擦除数据的擦除脉冲,并将擦除脉冲提供给所选存储单元。 控制电路通过在反向偏置方向上向非欧姆元件施加擦除脉冲的电压来执行数据擦除。
    • 6. 发明授权
    • Resistance change type memory
    • 电阻变化型存储器
    • US08324606B2
    • 2012-12-04
    • US12563470
    • 2009-09-21
    • Takayuki TsukamotoReika IchiharaHiroshi KannoKenichi Murooka
    • Takayuki TsukamotoReika IchiharaHiroshi KannoKenichi Murooka
    • H01L47/00
    • G11C11/5678G11C11/5685G11C13/0004G11C13/0007G11C13/0069G11C2213/72H01L27/101H01L27/2409H01L27/2481
    • A resistance change type memory of an aspect of the present invention including a first wiring configured to extend in a first direction, a second wiring configured to extend in a second direction crossing the first direction, a series circuit configured to connect to the first and second wirings, the series circuit including a non-ohmic element being more conductive in the first to second wiring direction than in the second to first direction and a resistance change type storage element in which data is stored according to a change of a resistance state, an energy supplying circuit configured to connect to the first wiring to supply energy to the first wiring, the energy being used to store the data in the resistance change type storage element, and a capacitance circuit configured to include a capacitive element and being connected to the second wiring.
    • 本发明的一个方面的电阻变化型存储器包括:构造成沿第一方向延伸的第一布线,沿与第一方向交叉的第二方向延伸的第二布线;串联电路,被配置为连接到第一和第二端 布线,包括在第一至第二布线方向上比在第二至第一方向上更加导电的非欧姆元件的串联电路和根据电阻状态的变化存储数据的电阻变化型存储元件, 能量供给电路,被配置为连接到所述第一布线以向所述第一布线供应能量,所述能量用于将所述数据存储在所述电阻变化型存储元件中;以及电容电路,被配置为包括电容元件并连接到所述第二布线 接线。