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1. 发明授权

US08450850B2 Thin-film transistor substrate and method of manufacturing the same 失效
标题翻译：薄膜晶体管基板及其制造方法
公开(公告)号：US08450850B2
公开(公告)日：2013-05-28
申请号：US13193413
申请日：2011-07-28
申请人： Hong Long Ning , Chang-Oh Jeong , Ji-Young Park , Sang-Gab Kim , Sung-Haeng Cho , Yeon-Hong Kim , Jin-Su Byun
发明人： Hong Long Ning , Chang-Oh Jeong , Ji-Young Park , Sang-Gab Kim , Sung-Haeng Cho , Yeon-Hong Kim , Jin-Su Byun
IPC分类号： H01L23/52
CPC分类号： H01L29/458 , B82Y10/00 , B82Y30/00 , H01L21/76877 , H01L27/124 , H01L29/41733 , H01L29/78684 , H01L51/0048 , H01L2221/1094
摘要： Provided are a thin-film transistor (TFT) substrate and a method of manufacturing the same. The method includes: forming a passivation film by forming an insulating film on a substrate; forming a photoresist pattern by forming a photoresist film on the passivation film, exposing the photoresist film to light, and developing the photoresist film; performing a first dry-etching by dry-etching the passivation film using the photoresist pattern as an etch mask; performing a baking to reduce a size of the photoresist pattern; performing a second dry-etching to form a contact hole by dry-etching the passivation film again using the photoresist pattern as a mask; removing the photoresist pattern; and forming a pixel electrode of a carbon composition that includes carbon nanotubes and/or graphene on a top surface of the passivation film.
摘要翻译：提供一种薄膜晶体管（TFT）基板及其制造方法。该方法包括：通过在基板上形成绝缘膜来形成钝化膜; 通过在钝化膜上形成光致抗蚀剂膜形成光致抗蚀剂图案，将光致抗蚀剂膜曝光并使光致抗蚀剂膜显影; 通过使用光致抗蚀剂图案作为蚀刻掩模来干蚀刻钝化膜来执行第一干蚀刻; 进行烘烤以减小光致抗蚀剂图案的尺寸; 通过使用光致抗蚀剂图案作为掩模再次干蚀刻钝化膜来进行第二次干蚀刻以形成接触孔; 去除光致抗蚀剂图案; 以及在钝化膜的顶表面上形成包括碳纳米管和/或石墨烯的碳组合物的像素电极。

2. 发明申请

US20120112346A1 THIN-FILM TRANSISTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：薄膜晶体管基板及其制造方法
公开(公告)号：US20120112346A1
公开(公告)日：2012-05-10
申请号：US13193413
申请日：2011-07-28
申请人： Hong Long NING , Chang-Oh Jeong , Ji-Young Park , Sang-Gab Kim , Sung-Haeng Cho , Yeon-Hong Kim , Jin-Su Byun
发明人： Hong Long NING , Chang-Oh Jeong , Ji-Young Park , Sang-Gab Kim , Sung-Haeng Cho , Yeon-Hong Kim , Jin-Su Byun
IPC分类号： H01L23/532 , B82Y40/00 , B82Y20/00 , H01L21/768
CPC分类号： H01L29/458 , B82Y10/00 , B82Y30/00 , H01L21/76877 , H01L27/124 , H01L29/41733 , H01L29/78684 , H01L51/0048 , H01L2221/1094
摘要： Provided are a thin-film transistor (TFT) substrate and a method of manufacturing the same. The method includes: forming a passivation film by forming an insulating film on a substrate; forming a photoresist pattern by forming a photoresist film on the passivation film, exposing the photoresist film to light, and developing the photoresist film; performing a first dry-etching by dry-etching the passivation film using the photoresist pattern as an etch mask; performing a baking to reduce a size of the photoresist pattern; performing a second dry-etching to form a contact hole by dry-etching the passivation film again using the photoresist pattern as a mask; removing the photoresist pattern; and forming a pixel electrode of a carbon composition that includes carbon nanotubes and/or graphene on a top surface of the passivation film.
摘要翻译：提供一种薄膜晶体管（TFT）基板及其制造方法。该方法包括：通过在基板上形成绝缘膜来形成钝化膜; 通过在钝化膜上形成光致抗蚀剂膜形成光致抗蚀剂图案，将光致抗蚀剂膜曝光并使光致抗蚀剂膜显影; 通过使用光致抗蚀剂图案作为蚀刻掩模来干蚀刻钝化膜来执行第一干蚀刻; 进行烘烤以减小光致抗蚀剂图案的尺寸; 通过使用光致抗蚀剂图案作为掩模再次干蚀刻钝化膜来进行第二次干蚀刻以形成接触孔; 去除光致抗蚀剂图案; 以及在钝化膜的顶表面上形成包括碳纳米管和/或石墨烯的碳组合物的像素电极。

3. 发明授权

US08653530B2 Thin film transistor array panel 失效
标题翻译：薄膜晶体管阵列面板
公开(公告)号：US08653530B2
公开(公告)日：2014-02-18
申请号：US13424278
申请日：2012-03-19
申请人： Pil Soon Hong , Gwui-Hyun Park , Jin-Su Byun , Sang Gab Kim
发明人： Pil Soon Hong , Gwui-Hyun Park , Jin-Su Byun , Sang Gab Kim
IPC分类号： H01L29/00
CPC分类号： H01L27/124 , H01L29/41733
摘要： The present invention relates to a thin film transistor array panel and a manufacturing method thereof that prevent disconnection of wiring due to misalignment of a mask, and simplify a process and reduce cost by reducing the number of masks. The thin film transistor array panel according to the disclosure includes a source electrode enclosing an outer part of the first contact hole and formed on the second insulating layer; a drain electrode enclosing an outer part of the second contact hole and formed on the second insulating layer; a first connection electrode connecting the source region of the semiconductor layer and the source electrode through the first contact hole; and a second connection electrode connecting the drain region of the semiconductor layer and the drain electrode through the second contact hole.
摘要翻译：薄膜晶体管阵列面板及其制造方法技术领域本发明涉及一种薄膜晶体管阵列面板及其制造方法，其能够防止由于掩模的未对准而使布线断开，并且通过减少掩模数来简化处理并降低成本。根据本发明的薄膜晶体管阵列面板包括：源电极，其包围第一接触孔的外部部分并形成在第二绝缘层上; 漏电极，其包围所述第二接触孔的外部部分并形成在所述第二绝缘层上; 第一连接电极，通过第一接触孔连接半导体层的源极区域和源极电极; 以及通过第二接触孔连接半导体层的漏极区域和漏极电极的第二连接电极。

4. 发明申请

US20130087800A1 THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF 失效
标题翻译：薄膜晶体管阵列及其制造方法
公开(公告)号：US20130087800A1
公开(公告)日：2013-04-11
申请号：US13424278
申请日：2012-03-19
申请人： Pil Soon HONG , Gwui-Hyun Park , Jin-Su Byun , Sang Gab Kim
发明人： Pil Soon HONG , Gwui-Hyun Park , Jin-Su Byun , Sang Gab Kim
IPC分类号： H01L27/15 , H01L33/08
CPC分类号： H01L27/124 , H01L29/41733
摘要： The present invention relates to a thin film transistor array panel and a manufacturing method thereof that prevent disconnection of wiring due to misalignment of a mask, and simplify a process and reduce cost by reducing the number of masks. The thin film transistor array panel according to the disclosure includes a source electrode enclosing an outer part of the first contact hole and formed on the second insulating layer; a drain electrode enclosing an outer part of the second contact hole and formed on the second insulating layer; a first connection electrode connecting the source region of the semiconductor layer and the source electrode through the first contact hole; and a second connection electrode connecting the drain region of the semiconductor layer and the drain electrode through the second contact hole.
摘要翻译：薄膜晶体管阵列面板及其制造方法技术领域本发明涉及一种薄膜晶体管阵列面板及其制造方法，其能够防止由于掩模的未对准而使布线断开，并且通过减少掩模数来简化处理并降低成本。根据本发明的薄膜晶体管阵列面板包括：源电极，其包围第一接触孔的外部部分并形成在第二绝缘层上; 漏电极，其包围所述第二接触孔的外部部分并形成在所述第二绝缘层上; 第一连接电极，通过第一接触孔连接半导体层的源极区域和源极电极; 以及通过第二接触孔连接半导体层的漏极区域和漏极电极的第二连接电极。

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