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1. 发明授权

US09025356B2 Fly-over conductor segments in integrated circuits with successive load devices along a signal path 有权
标题翻译：集成电路中的飞越导体段，沿着信号路径连续的负载装置
公开(公告)号：US09025356B2
公开(公告)日：2015-05-05
申请号：US13221081
申请日：2011-08-30
申请人： Hsiao-Wen Lu , Wei-Jer Hsieh , Chiting Cheng , Chung-Cheng Chou , Jonathan Tsung-Yung Chang
发明人： Hsiao-Wen Lu , Wei-Jer Hsieh , Chiting Cheng , Chung-Cheng Chou , Jonathan Tsung-Yung Chang
IPC分类号： G11C5/06 , G11C7/10 , G11C11/00 , G11C11/413
CPC分类号： G11C5/063 , G11C11/413 , Y10T307/445
摘要： The propagation delay of a signal through multiple load devices coupled sequentially along a conductor is improved by separating a subset of the load devices that is more distant from the signal source, and coupling the more distant subset to the signal through a fly-over conductor that bypasses the subset that is nearer to the signal source. The technique is applicable to subsets of bit cells in a random access memory (SRAM) coupled to a given word line, or to word line decoder gates coupled sequentially to a strobe signal, as well as other circuits wherein load devices selectable as a group can be divided into subsets by proximity to the signal source. In an SRAM layout with multiple levels, different metal deposition layers carry the conductor legs between the load devices versus the fly-over conductor bypassing the nearer subset.
摘要翻译：通过分离距离信号源更远的负载装置的子集，并通过飞越导体将更远的子集耦合到信号，改善了通过沿导体顺序耦合的多个负载装置的信号的传播延迟，绕过更靠近信号源的子集。该技术适用于耦合到给定字线的随机存取存储器（SRAM）中的位单元的子集，或者适用于顺序耦合到选通信号的字线解码器门，以及其他可选择作为一组的负载装置的电路通过靠近信号源将其划分为子集。在具有多个级别的SRAM布局中，不同的金属沉积层承载负载装置之间的导体腿与绕过更近的子集的飞越导体。

2. 发明申请

US20130051128A1 FLY-OVER CONDUCTOR SEGMENTS IN INTEGRATED CIRCUITS WITH SUCCESSIVE LOAD DEVICES ALONG A SIGNAL PATH 有权
标题翻译：集成电路中的FLY-OVER导体部分与信号路径中的连续负载设备
公开(公告)号：US20130051128A1
公开(公告)日：2013-02-28
申请号：US13221081
申请日：2011-08-30
申请人： Hsiao-Wen Lu , Wei-Jer Hsieh , Chiting Cheng , Chung-Cheng Chou , Jonathan Tsung-Yung Chang
发明人： Hsiao-Wen Lu , Wei-Jer Hsieh , Chiting Cheng , Chung-Cheng Chou , Jonathan Tsung-Yung Chang
IPC分类号： G11C11/00 , H02J1/00 , H03H11/26 , G11C7/00
CPC分类号： G11C5/063 , G11C11/413 , Y10T307/445
摘要： The propagation delay of a signal through multiple load devices coupled sequentially along a conductor is improved by separating a subset of the load devices that is more distant from the signal source, and coupling the more distant subset to the signal through a fly-over conductor that bypasses the subset that is nearer to the signal source. The technique is applicable to subsets of bit cells in a random access memory (SRAM) coupled to a given word line, or to word line decoder gates coupled sequentially to a strobe signal, as well as other circuits wherein load devices selectable as a group can be divided into subsets by proximity to the signal source. In an SRAM layout with multiple levels, different metal deposition layers carry the conductor legs between the load devices versus the fly-over conductor bypassing the nearer subset.
摘要翻译：通过分离距离信号源更远的负载装置的子集，并通过飞越导体将更远的子集耦合到信号，改善了通过沿导体顺序耦合的多个负载装置的信号的传播延迟，绕过更靠近信号源的子集。该技术适用于耦合到给定字线的随机存取存储器（SRAM）中的位单元的子集，或者适用于顺序耦合到选通信号的字线解码器门，以及其他可选择作为一组的负载装置的电路通过靠近信号源将其划分为子集。在具有多个级别的SRAM布局中，不同的金属沉积层承载负载装置之间的导体腿与绕过更近的子集的飞越导体。

3. 发明授权

US09064550B2 Method and apparatus for word line suppression 有权
标题翻译：用于字线抑制的方法和装置
公开(公告)号：US09064550B2
公开(公告)日：2015-06-23
申请号：US13279375
申请日：2011-10-24
申请人： Jonathan Tsung-Yung Chang , Chiting Cheng , Chien-Kuo Su , Chung-Cheng Chou , Jack Liu
发明人： Jonathan Tsung-Yung Chang , Chiting Cheng , Chien-Kuo Su , Chung-Cheng Chou , Jack Liu
IPC分类号： G11C11/00 , G11C8/08 , G11C11/418
CPC分类号： G11C8/08 , G11C11/418
摘要： A memory access operation on a bit cell of a digital memory, e.g., a static random access memory (SRAM), is assisted by reducing the word line control voltage for reading and boosting it for writing, thus improving data integrity. The bit cell has cross coupled inverters for storing and retrieving a logic state via bit line connections through a passing gate transistor controlled by the word line. A level of a word line signal controlling the passing gate transistor is shifted from a first voltage value to a higher second voltage value to begin a memory access cycle. The level of the word line signal is shifted from the second voltage value to a third voltage value less than the second voltage value during the access cycle. The word line signal is maintained at the third voltage value for a time interval during the access cycle.
摘要翻译：数字存储器的位单元（例如静态随机存取存储器（SRAM））上的存储器访问操作通过减少字线控制电压来进行辅助，用于读取和提升其用于写入，从而提高数据完整性。位单元具有交叉耦合的反相器，用于经由位线连接通过由字线控制的通过栅极晶体管来存储和取回逻辑状态。控制通过栅极晶体管的字线信号的电平从第一电压值移位到较高的第二电压值，以开始存储器访问周期。在访问周期期间，字线信号的电平从第二电压值移位到小于第二电压值的第三电压值。在访问周期期间，字线信号保持在第三电压值一段时间间隔。

4. 发明申请

US20120307574A1 SRAM READ and WRITE Assist Apparatus 有权
标题翻译： SRAM读写功能
公开(公告)号：US20120307574A1
公开(公告)日：2012-12-06
申请号：US13149611
申请日：2011-05-31
申请人： Chiting Cheng , Chung-Cheng Chou , Jonathan Tsung-Yung Chang
发明人： Chiting Cheng , Chung-Cheng Chou , Jonathan Tsung-Yung Chang
IPC分类号： G11C7/00
CPC分类号： G11C11/419
摘要： A SRAM READ and WRITE assist apparatus comprises a bit line voltage tracking block, a READ assist timer, a READ assist unit, a WRITE assist unit a WRITE control unit. The bit line voltage tracking block detects a voltage on a tracking bit line coupled to a plurality of tracking memory cells. In response to the voltage drop on the tracking bit line, the READ assist timer generates a READ assist pulse. When the READ assist pulse has a logic high state, an activated word line is pulled down to a lower voltage. Such a lower voltage helps to improve the robustness of SRAM memory circuits so as to avoid READ and WRITE failures.
摘要翻译： SRAM读写辅助装置包括位线电压跟踪块，READ辅助定时器，READ辅助单元，WRITE辅助单元，WRITE控制单元。位线电压跟踪块检测耦合到多个跟踪存储器单元的跟踪位线上的电压。响应于跟踪位线上的电压降，READ辅助定时器产生READ辅助脉冲。当READ辅助脉冲具有逻辑高电平状态时，激活的字线被下拉到较低的电压。这样较低的电压有助于提高SRAM存储器电路的鲁棒性，以避免读取和写入故障。

5. 发明授权

US08630132B2 SRAM read and write assist apparatus 有权
标题翻译： SRAM读写辅助装置
公开(公告)号：US08630132B2
公开(公告)日：2014-01-14
申请号：US13149611
申请日：2011-05-31
申请人： Chiting Cheng , Chung-Cheng Chou , Jonathan Tsung-Yung Chang
发明人： Chiting Cheng , Chung-Cheng Chou , Jonathan Tsung-Yung Chang
IPC分类号： G11C7/22
CPC分类号： G11C11/419
摘要： A SRAM READ and WRITE assist apparatus comprises a bit line voltage tracking block, a READ assist timer, a READ assist unit, a WRITE assist unit a WRITE control unit. The bit line voltage tracking block detects a voltage on a tracking bit line coupled to a plurality of tracking memory cells. In response to the voltage drop on the tracking bit line, the READ assist timer generates a READ assist pulse. When the READ assist pulse has a logic high state, an activated word line is pulled down to a lower voltage. Such a lower voltage helps to improve the robustness of SRAM memory circuits so as to avoid READ and WRITE failures.
摘要翻译： SRAM读写辅助装置包括位线电压跟踪块，READ辅助定时器，READ辅助单元，WRITE辅助单元，WRITE控制单元。位线电压跟踪块检测耦合到多个跟踪存储器单元的跟踪位线上的电压。响应于跟踪位线上的电压降，READ辅助定时器产生READ辅助脉冲。当READ辅助脉冲具有逻辑高电平状态时，激活的字线被下拉到较低的电压。这样较低的电压有助于提高SRAM存储器电路的鲁棒性，以避免读取和写入故障。

6. 发明授权

US08848461B2 Memory cell having flexible read/write assist and method of using 有权
标题翻译：存储单元具有灵活的读/写辅助和使用方法
公开(公告)号：US08848461B2
公开(公告)日：2014-09-30
申请号：US13464489
申请日：2012-05-04
申请人： Jonathan Tsung-Yung Chang , Kun-Hsi Li , Chiting Cheng
发明人： Jonathan Tsung-Yung Chang , Kun-Hsi Li , Chiting Cheng
IPC分类号： G11C7/22
CPC分类号： G11C11/419 , G11C11/41 , G11C29/028 , G11C29/56 , G11C2029/5002 , H01L21/78
摘要： A semiconductor device includes at least one memory cell die. The at least one memory cell die includes a data storage unit. The at least one memory cell die includes at least one read assist enabling unit electrically connected to the data storage unit. The at least one read assist enabling unit configured to lower a voltage of a word line. The memory cell die also includes at least one write assist enabling unit electrically connected to the data storage unit. The at least one write assist enabling unit configured to supply a negative voltage to at least one of a bit line or a bit line bar.
摘要翻译：半导体器件包括至少一个存储单元管芯。至少一个存储单元管芯包括数据存储单元。至少一个存储单元管芯包括电连接到数据存储单元的至少一个读辅助使能单元。所述至少一个读辅助使能单元被配置为降低字线的电压。存储单元管芯还包括电连接到数据存储单元的至少一个写辅助使能单元。所述至少一个写入辅助使能单元被配置为向位线或位线条中的至少一个提供负电压。

7. 发明授权

US08958232B2 Method and apparatus for read assist to compensate for weak bit 有权
标题翻译：用于读取辅助补偿弱点的方法和装置
公开(公告)号：US08958232B2
公开(公告)日：2015-02-17
申请号：US13437081
申请日：2012-04-02
申请人： Jonathan Tsung-Yung Chang , Cheng Hung Lee , Chung-Cheng Chou , Hung-Jen Liao , Bin-Hau Lo
发明人： Jonathan Tsung-Yung Chang , Cheng Hung Lee , Chung-Cheng Chou , Hung-Jen Liao , Bin-Hau Lo
IPC分类号： G11C17/00
CPC分类号： G11C7/12 , G11C7/067 , G11C11/412 , G11C11/419
摘要： A memory assist apparatus includes a detection circuit and a compensation circuit. The detection circuit is configured to provide a detection signal indicating whether a bit line configured to provide read access to a data bit stored at a memory bit cell has a voltage below a predetermined threshold. The compensation circuit is configured to pull down the voltage of the bit line if the detection signal indicates that the voltage of the bit line is below the predetermined threshold.
摘要翻译：记忆辅助装置包括检测电路和补偿电路。检测电路被配置为提供一个检测信号，该检测信号指示被配置为对存储在存储位单元中的数据位提供读取访问的位线是否具有低于预定阈值的电压。如果检测信号指示位线的电压低于预定阈值，则补偿电路被配置为下拉位线的电压。

8. 发明授权

US08559251B2 Memory circuit and method of writing datum to memory circuit 有权
标题翻译：存储电路和将数据写入存储电路的方法
公开(公告)号：US08559251B2
公开(公告)日：2013-10-15
申请号：US13354884
申请日：2012-01-20
申请人： Chih-Yu Lin , Wei Min Chan , Yen-Huei Chen , Hung-Jen Liao , Jonathan Tsung-Yung Chang
发明人： Chih-Yu Lin , Wei Min Chan , Yen-Huei Chen , Hung-Jen Liao , Jonathan Tsung-Yung Chang
IPC分类号： G11C7/10
CPC分类号： G11C11/419
摘要： A circuit includes a first node, a second node, a memory cell, a first data line, a second data line, and a write driver. The memory cell is coupled to the first node and the second node and powered by a first voltage at the first node and a second voltage at the second node. The first data line and the second data line are coupled to the memory cell. The write driver has a third node carrying a third voltage less than the first voltage during a write operation. The write deriver is coupled to the first data line and the second data line and configured to, during a write operation, selectively coupling one of the first data line and the second data line to the third node and coupling the other one of the first data line and the second data line to the first node.
摘要翻译：电路包括第一节点，第二节点，存储器单元，第一数据线，第二数据线和写驱动器。存储器单元耦合到第一节点和第二节点，并由第一节点处的第一电压和第二节点处的第二电压供电。第一数据线和第二数据线耦合到存储器单元。写入驱动器具有在写入操作期间承载小于第一电压的第三电压的第三节点。写引导器耦合到第一数据线和第二数据线，并且被配置为在写操作期间，选择性地将第一数据线和第二数据线之一耦合到第三节点，并将第一数据中的另一个耦合线和第二条数据线到第一个节点。

9. 发明授权

US08713491B2 Pre-colored methodology of multiple patterning 有权
标题翻译：多色图案的预色方法
公开(公告)号：US08713491B2
公开(公告)日：2014-04-29
申请号：US13607946
申请日：2012-09-10
申请人： Yen-Huei Chen , Hung-Jen Liao , Jonathan Tsung-Yung Chang
发明人： Yen-Huei Chen , Hung-Jen Liao , Jonathan Tsung-Yung Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： Some embodiments relate to a method of pre-coloring word lines and control lines within an SRAM integrated chip design to avoid timing delays that result from processing variations introduced through multiple patterning lithography processes. The method is performed by generating a graphical IC layout file having an SRAM circuit with a plurality of word lines and Y-control lines. The word lines and Y-control lines are assigned a color during decomposition. The word lines and Y-control lines are further pre-colored in a manner that deliberately assigns the pre-colored data to a same mask. Therefore, during mask building, data associated with pre-colored word and Y-control lines is sent to a same mask, regardless of the colors that are assigned to the data. By assigning word and Y-control lines to a same mask through pre-coloring, processing variations between the word and Y-control lines are minimized, thereby mitigating timing variations in an SRAM circuit.
摘要翻译：一些实施例涉及在SRAM集成芯片设计中预先着色字线和控制线的方法，以避免由通过多次图案化光刻工艺引入的处理变化而产生的定时延迟。该方法通过生成具有多个字线和Y控制线的SRAM电路的图形IC布局文件来执行。在分解过程中，字线和Y控制线被分配一个颜色。字线和Y控制线进一步预先着色，以故意将预色数据分配给相同的掩码。因此，在面具构建期间，与预色彩字和Y控制线相关联的数据被发送到相同的掩码，而不管分配给数据的颜色如何。通过预分色将字和Y控制线分配给相同的掩码，字和Y控制线之间的处理变化被最小化，从而减轻SRAM电路中的定时变化。

10. 发明授权

US08693265B2 Data inversion for dual-port memory 有权
标题翻译：双端口存储器的数据反转
公开(公告)号：US08693265B2
公开(公告)日：2014-04-08
申请号：US13552692
申请日：2012-07-19
申请人： Tzu-Kuei Lin , Jonathan Tsung-Yung Chang , Hung-Jen Liao , Yen-Huei Chen , Jhon Jhy Liaw
发明人： Tzu-Kuei Lin , Jonathan Tsung-Yung Chang , Hung-Jen Liao , Yen-Huei Chen , Jhon Jhy Liaw
IPC分类号： G11C16/04
CPC分类号： G11C7/1006 , G11C7/1075 , G11C8/16 , G11C11/412
摘要： A semiconductor memory includes first and second memory storage latches each including first and second ports. A first pair of bit lines is coupled to the first ports, and a second pair of bit lines is coupled to the second ports. The first and second pairs of bit lines are twisted between the first and second memory storage latches. A first sense amplifier is coupled to the first pair of bit lines for outputting data, and a second sense amplifier is coupled to the second pair of bit lines for outputting an intermediate data signal. Output logic circuitry is coupled to an output of the second sense amplifier and is configured to output data based on the intermediate data signal and a control signal that identifies if the data is being read from the first memory storage latch or from the second memory storage latch.
摘要翻译：半导体存储器包括每个包括第一和第二端口的第一和第二存储器存储器锁存器。第一对位线耦合到第一端口，并且第二对位线耦合到第二端口。第一和第二对位线在第一和第二存储器锁存器之间被扭转。第一读出放大器耦合到第一对位线，用于输出数据，第二读出放大器耦合到第二对位线，用于输出中间数据信号。输出逻辑电路耦合到第二读出放大器的输出，并且被配置为基于中间数据信号和控制信号输出数据，该控制信号识别数据是否正在从第一存储器存储锁存器或第二存储器存储器锁存器中读取。

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