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1. 发明授权

US09564218B2 Associative memory circuit 有权
标题翻译：关联存储器电路
公开(公告)号：US09564218B2
公开(公告)日：2017-02-07
申请号：US14601216
申请日：2015-01-20
申请人： Huazhong University of Science and Technology
发明人： Xiangshui Miao , Yi Li , Lei Xu , Yingpeng Zhong
IPC分类号： G11C15/04 , G11C11/54 , G11C13/00
CPC分类号： G11C15/046 , G11C11/54 , G11C13/0007
摘要： An associative memory circuit including a first memristor, a second memristor, a fixed value resistor R, and an operational comparator. One terminal of the first memristor is a first input terminal of the associative memory circuit, and the other terminal of the first memristor is connected to a first input terminal of the operational comparator. One terminal of the second memristor is a second input terminal of the associative memory circuit, and the other terminal of the second memristor is connected to the first input terminal of the operational comparator. One terminal of the fixed value resistor is connected to the first input terminal of the operational comparator, and the other terminal of the fixed value resistor is connected to the ground. A second input terminal of the operational comparator is connected to a reference voltage.
摘要翻译：一种包括第一忆阻器，第二忆阻器，固定值电阻器R和操作比较器的关联存储器电路。第一忆阻器的一个端子是相关存储器电路的第一输入端，并且第一忆阻器的另一端连接到操作比较器的第一输入端。第二忆阻器的一个端子是关联存储器电路的第二输入端，并且第二忆阻器的另一端连接到运算比较器的第一输入端。固定值电阻的一端连接到运算比较器的第一输入端，固定值电阻的另一端连接到地。操作比较器的第二输入端连接到参考电压。

2. 发明授权

US09369130B2 Nonvolatile logic gate circuit based on phase change memory 有权
标题翻译：基于相变存储器的非易失逻辑门电路
公开(公告)号：US09369130B2
公开(公告)日：2016-06-14
申请号：US14706004
申请日：2015-05-07
申请人： Huazhong University of Science and Technology
发明人： Xiangshui Miao , Yi Li , Yingpeng Zhong , Lei Xu , Huajun Sun , Xiaomin Cheng
IPC分类号： H03K19/003 , G11C13/00 , H03K19/173 , H03K19/20 , H03K19/177
CPC分类号： H03K19/00346 , G11C13/0004 , G11C13/004 , H03K19/1733 , H03K19/17724 , H03K19/20
摘要： A nonvolatile logic gate circuit based on phase change memories, including a first phase change memory, a second phase change memory, a first controllable switch element and a first resistor, wherein a first end of the first phase change memory serves as a first input end of an AND gate circuit, a first end of the second phase change memory serves as a second input end of the AND gate circuit, a first end of the first controllable switch element is connected to a second end of the first phase change memory, a second end of the first controllable switch element is grounded; one end of the first resistor is connected to the first end of the second phase change memory, the other end of the first resistor is grounded; and the first end of the second phase change memory serves as an output end of the AND gate circuit.
摘要翻译：一种基于相变存储器的非易失性逻辑门电路，包括第一相变存储器，第二相变存储器，第一可控开关元件和第一电阻器，其中第一相变存储器的第一端用作第一输入端和门电路的第一端，第二相变存储器的第一端用作与门电路的第二输入端，第一可控开关元件的第一端连接到第一相变存储器的第二端，第一可控开关元件的第二端接地; 第一电阻器的一端连接到第二相变存储器的第一端，第一电阻器的另一端接地; 并且第二相变存储器的第一端用作与门电路的输出端。

3. 发明授权

US09418733B2 Joint short-time and long-time storage device and storage method thereof 有权
标题翻译：联合短时和长时间存储设备及其存储方法
公开(公告)号：US09418733B2
公开(公告)日：2016-08-16
申请号：US14800693
申请日：2015-07-15
申请人： Huazhong University of Science and Technology
发明人： Xiangshui Miao , Yi Li , Yingpeng Zhong , Lei Xu , Huajun Sun , Xiaohua Xu
IPC分类号： G11C11/00 , G11C13/00 , H01L45/00 , G11C14/00 , G11C11/54
CPC分类号： G11C13/0004 , G11C11/005 , G11C11/54 , G11C13/0002 , G11C13/0011 , G11C13/0033 , G11C13/0035 , G11C13/0069 , G11C13/0097 , G11C14/00 , G11C2013/0092 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/142 , H01L45/143 , H01L45/144
摘要： A joint short-time and long-time storage device, including a first electrode layer, a functional material layer connected to the first electrode layer, and a second electrode layer connected to the functional material layer. The first electrode layer is made of inert conductive metal, the second electrode layer is made of active conductive metal, and the functional material layer is made of chalcogenide.
摘要翻译：一种联合的短时和长时间存储装置，包括第一电极层，连接到第一电极层的功能材料层和连接到功能材料层的第二电极层。第一电极层由惰性导电金属制成，第二电极层由有源导电金属制成，功能材料层由硫族化物制成。

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