专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20200280318A1 DITHERING FOR SPUR REDUCTION IN LOCAL OSCILLATOR GENERATION 审中-公开
公开(公告)号：US20200280318A1
公开(公告)日：2020-09-03
申请号：US16646746
申请日：2017-09-12
申请人： INTEL IP CORPORATION
发明人： Christoph S. Preissi , Peter Preyler , Thomas Mayer
IPC分类号： H03L7/081 , H03L7/07 , H03L7/16 , G06F1/025
摘要： Method, systems, and circuitries are provided for generating an output signal with reduced spurs by dithering. A method to generate an output signal having a desired frequency based on a reference signal having a reference frequency includes receiving a desired phase shift between a next cycle of the output signal with respect to a next cycle of the reference signal. A mapping between respective code words and phase shifts is read. A first codeword mapped to a first phase shift that is lower in value to the desired phase shift is identified. A second codeword mapped to a second phase shift that is higher in value to the desired phase shift is identified. The method includes selecting either the first codeword or the second codeword and generating the output signal based on the selected codeword.

2. 发明授权

US10979056B2 Dithering for spur reduction in local oscillator generation 有权
公开(公告)号：US10979056B2
公开(公告)日：2021-04-13
申请号：US16646746
申请日：2017-09-12
申请人： INTEL IP CORPORATION
发明人： Christoph S. Preissel , Peter Preyler , Thomas Mayer
IPC分类号： H03L7/081 , G06F1/025 , H03L7/07 , H03L7/16
摘要： Method, systems, and circuitries are provided for generating an output signal with reduced spurs by dithering. A method to generate an output signal having a desired frequency based on a reference signal having a reference frequency includes receiving a desired phase shift between a next cycle of the output signal with respect to a next cycle of the reference signal. A mapping between respective code words and phase shifts is read. A first codeword mapped to a first phase shift that is lower in value to the desired phase shift is identified. A second codeword mapped to a second phase shift that is higher in value to the desired phase shift is identified. The method includes selecting either the first codeword or the second codeword and generating the output signal based on the selected codeword.

3. 发明授权

US10298243B2 System and a method for determining a correction for an output value of a time-to-digital converter within a phase-locked loop 有权
公开(公告)号：US10298243B2
公开(公告)日：2019-05-21
申请号：US15575830
申请日：2016-06-08
申请人： Intel IP Corporation
发明人： Thomas Mayer
IPC分类号： H03L7/06 , H03L7/099 , H03L7/197 , H03L7/091 , H04B1/02
摘要： A system for determining a correction for an output value of a time-to-digital converter within a phase-locked loop is provided. The output value relates to a time difference between an input signal and a reference signal supplied to the time-to-digital converter. The system includes a digitally-controlled oscillator configured to generate a first signal independently from the output signal. The first signal has a first frequency different from an integer multiple of a reference frequency of the reference signal. The system further includes a frequency divider configured to generate the input signal for the time-to-digital converter based on the first signal. The input signal has a second frequency being a fraction of the first frequency. Further, the system includes a processing unit configured to calculate the correction using a distribution of output values of multiple time differences.

4. 发明授权

US09584139B2 Phase tracker for a phase locked loop 有权
标题翻译：相位跟踪器用于锁相环
公开(公告)号：US09584139B2
公开(公告)日：2017-02-28
申请号：US14494718
申请日：2014-09-24
申请人： Intel IP Corporation
发明人： Christian Wicpalek , Thomas Mayer , Andreas Mayer , Thorsten Tracht
IPC分类号： H03L7/08 , H03L7/085 , G04F10/00 , H03L7/197
CPC分类号： H03L7/085 , G04F10/005 , H03L7/1976
摘要： A phase locked loop includes a feedforward path receiving a reference signal having a reference frequency and outputting an output signal having an output frequency that is a function of the reference signal and a feedback signal. The phase locked loop further includes a feedback path having a divider circuit associated therewith that is configured to receive the output signal and generate the feedback signal having a reduced frequency based on a divide value of the divider circuit. The feedback signal is supplied to the feedforward path. The phase locked loop also includes a modulator circuit configured to receive modulation data and provide a divider control signal to the divider circuit to control the divide value thereof, and a phase tracker circuit configured to determine an amount of phase drift from an initial phase value of the output signal due to an interruption in a locked state of the phase locked loop.
摘要翻译：锁相环包括接收具有参考频率的参考信号的前馈路径，并输出具有作为参考信号和反馈信号的函数的输出频率的输出信号。锁相环还包括具有与其相关联的分频器电路的反馈路径，其被配置为接收输出信号并且基于分频器电路的除法产生具有降低的频率的反馈信号。反馈信号被提供给前馈路径。锁相环还包括配置成接收调制数据并将分频器控制信号提供给分频器电路以控制其分频值的调制器电路，以及相位跟踪器电路，被配置为从相位漂移的初始相位值该输出信号由于锁相环中的锁定状态而中断。

5. 发明授权

US09537585B2 Circuit, an integrated circuit, a transmitter, a receiver, a transceiver, a method for obtaining calibration data and a method for generating a local oscillator signal 有权
标题翻译：电路，集成电路，发送器，接收器，收发器，用于获得校准数据的方法以及用于产生本地振荡器信号的方法
公开(公告)号：US09537585B2
公开(公告)日：2017-01-03
申请号：US14620488
申请日：2015-02-12
申请人： Intel IP Corporation
发明人： Thomas Mayer , Stefan Tertinek , Peter Preyler
IPC分类号： H04B17/21 , H04B1/62 , H03L7/197
CPC分类号： H04B17/21 , H03L7/1976 , H04B1/62
摘要： A circuit according to an example includes a digital-to-time converter and a signal processing circuit coupled to the digital-to-time converter and configured to generate a processed signal derived from a signal provided to the signal processing circuit, the processed signal including a predetermined phase relation with respect to the signal provided to the signal processing circuit, wherein the circuit is configured to receive a reference signal and to generate an output signal based on the received reference signal. The a measurement circuit is configured to measure a delay between the output signal and the reference signal, wherein the output of the digital-to-time converter is coupled to a memory configured to store calibration data of the digital-to-time converter based on the measured delay.
摘要翻译：根据示例的电路包括数字 - 时间转换器和耦合到数字 - 时间转换器并被配置为产生从提供给信号处理电路的信号导出的处理信号的信号处理电路，处理信号包括相对于提供给信号处理电路的信号的预定相位关系，其中电路被配置为接收参考信号并且基于接收到的参考信号产生输出信号。测量电路被配置为测量输出信号和参考信号之间的延迟，其中数字 - 时间转换器的输出耦合到存储器，该存储器被配置为存储数字 - 时间转换器的校准数据，基于测量延迟。

6. 发明申请

US20160182072A1 NOISE-SHAPING CIRCUIT, DIGITAL-TO-TIME CONVERTER, ANALOG-TO-DIGITAL CONVERTER, DIGITAL-TO-ANALOG CONVERTER FREQUENCY SYNTHESIZER, TRANSMITTER, RECEIVER, TRANSCEIVER, METHOD FOR SHAPING NOISE IN AN INPUT SIGNAL 有权
标题翻译：噪声形成电路，数字到时间转换器，模拟数字转换器，数字到模拟转换器频率合成器，发送器，接收器，收发器，在输入信号中形成噪声的方法
公开(公告)号：US20160182072A1
公开(公告)日：2016-06-23
申请号：US14856854
申请日：2015-09-17
申请人： Intel IP Corporation
发明人： Peter Preyler , Thomas Mayer , Stefan Tertinek
IPC分类号： H03M1/06 , H03L7/20 , H03M1/66
CPC分类号： H03L7/20 , H03L7/16 , H03L2207/50 , H03M3/33 , H03M3/436
摘要： A noise shaping circuit according to an example includes a forward signal path configured to generate an output signal based on an input signal, a feedback signal path configured to feed back a feedback signal based on the output signal to the forward signal path, and a dither generator configured to generate a dither signal and to couple the dither signal into the forward signal path to modify the input signal and into the feedback signal path. Employing a noise shaping circuit according to an example may improve an overall noise performance.
摘要翻译：根据示例的噪声整形电路包括被配置为基于输入信号生成输出信号的正向信号路径，被配置为基于输出信号将反馈信号反馈到前向信号路径的反馈信号路径，以及抖动发生器被配置为产生抖动信号并将抖动信号耦合到正向信号路径中以修改输入信号并进入反馈信号路径。使用根据示例的噪声整形电路可以提高整体噪声性能。

7. 发明申请

US20160094237A1 CIRCUIT, AN INTEGRATED CIRCUIT, A TRANSMITTER, A RECEIVER, A TRANSCEIVER, A METHOD FOR GENERATING A PROCESSED OSCILLATOR SIGNAL, AN APPARATUS FOR GENERATING A PROCESSED OSCILLATOR SIGNAL, AND SOFTWARE-RELATED IMPLEMENTATIONS 有权
标题翻译：电路，集成电路，发送器，接收器，收发器，产生处理的振荡器信号的方法，用于生成加工的振荡器信号的装置和与软件相关的实现
公开(公告)号：US20160094237A1
公开(公告)日：2016-03-31
申请号：US14832342
申请日：2015-08-21
申请人： Intel IP Corporation
发明人： Stefan Tertinek , Peter Preyler , Thomas Mayer
IPC分类号： H03M1/06 , H04B1/403 , H03M1/66
CPC分类号： H03M1/10 , G06F1/0321 , H03L7/00 , H03L2207/50 , H03M1/82
摘要： A circuit according to an example includes a digital-to-time converter configured to receive an oscillator signal and to generate a processed oscillator signal based on the received oscillator signal in response to a control signal, and a time-interleaved control circuit configured to generate the control signal based on a time-interleaved technique.
摘要翻译：根据示例的电路包括数字 - 时间转换器，其被配置为响应于控制信号接收振荡器信号并且基于接收的振荡器信号产生经处理的振荡器信号，以及时间交织控制电路，被配置为产生基于时间交织技术的控制信号。

8. 发明授权

US10804908B2 Clock generator, phase locked loop, apparatus, method and computer program for generating a clock signal, transceiver, and mobile terminal 有权
公开(公告)号：US10804908B2
公开(公告)日：2020-10-13
申请号：US16348184
申请日：2017-11-07
申请人： Intel IP Corporation
发明人： Thomas Mayer , Christian Wicpalek
IPC分类号： G05F1/04 , H03K3/00 , H03L7/08 , G04F10/00 , G06F1/08 , G06F1/10 , G06F7/58 , H03K3/84 , H03L7/091 , H03L7/099 , G06F1/04 , H03L7/085 , H03L7/197
摘要： Examples provide a system, a phase locked loop, an apparatus, a method and a computer program for generating a clock signal, a transceiver, and a mobile terminal. A system comprises clock generator (10) configured to output provide a clock signal having a predefined average clock rate, a reference signal generator (14) configured to provide a reference signal, and a clock divider (16) configured to divide the reference signal to generate the clock signal, wherein a time difference between a clock cycles and a subsequent clock cycle of the clock signal is irregular.

9. 发明授权

US09768809B2 Digital-to-time converter spur reduction 有权
公开(公告)号：US09768809B2
公开(公告)日：2017-09-19
申请号：US14318829
申请日：2014-06-30
申请人： Intel IP Corporation
发明人： Stefan Tertinek , Peter Preyler , Thomas Mayer
IPC分类号： H04B1/00 , H04B7/06 , H04W88/06 , H04L27/14 , G04F10/00
CPC分类号： H04B1/0082 , G04F10/005
摘要： This application discusses, among other things, apparatus and methods for improving spurious frequency performance of digital-to-time converters (DTCs). In an example, a method can include receiving a code at selection logic of a digital-to-time converter at a first instant, selecting a first delay path of the DTC to provide a delay associated with the code, associating a second delay path with the code, receiving the code at the selection logic at a second instant, and selecting the second delay path of the DTC to provide the delay associated with the code.

10. 发明申请

US20160087639A1 PHASE TRACKER FOR A PHASE LOCKED LOOP 有权
标题翻译：相位锁相环的相位跟踪器
公开(公告)号：US20160087639A1
公开(公告)日：2016-03-24
申请号：US14494718
申请日：2014-09-24
申请人： Intel IP Corporation
发明人： Christian Wicpalek , Thomas Mayer , Andreas Mayer , Thorsten Tracht
IPC分类号： H03L7/085 , G04F10/00
CPC分类号： H03L7/085 , G04F10/005 , H03L7/1976
摘要： A phase locked loop includes a feedforward path receiving a reference signal having a reference frequency and outputting an output signal having an output frequency that is a function of the reference signal and a feedback signal. The phase locked loop further includes a feedback path having a divider circuit associated therewith that is configured to receive the output signal and generate the feedback signal having a reduced frequency based on a divide value of the divider circuit. The feedback signal is supplied to the feedforward path. The phase locked loop also includes a modulator circuit configured to receive modulation data and provide a divider control signal to the divider circuit to control the divide value thereof, and a phase tracker circuit configured to determine an amount of phase drift from an initial phase value of the output signal due to an interruption in a locked state of the phase locked loop.
摘要翻译：锁相环包括接收具有参考频率的参考信号的前馈路径，并输出具有作为参考信号和反馈信号的函数的输出频率的输出信号。锁相环还包括具有与其相关联的分频器电路的反馈路径，其被配置为接收输出信号并且基于分频器电路的除法产生具有降低的频率的反馈信号。反馈信号被提供给前馈路径。锁相环还包括配置成接收调制数据并将分频器控制信号提供给分频器电路以控制其分频值的调制器电路，以及相位跟踪器电路，被配置为从相位漂移的初始相位值该输出信号由于锁相环中的锁定状态而中断。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式