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1. 发明授权

US11656650B2 Model generation system, model generation method, and model generation program 有权
公开(公告)号：US11656650B2
公开(公告)日：2023-05-23
申请号：US16485475
申请日：2017-02-14
申请人： NEC Corporation
发明人： Shinji Nakadai , Hao Zhang
IPC分类号： G06F1/00 , G06F1/025 , G06N20/10 , G06F17/14 , G06F30/20 , G06F111/10
CPC分类号： G06F1/025 , G06F17/14 , G06F30/20 , G06N20/10 , G06F2111/10
摘要： The kernel function generation unit 81 defines a first kernel function by using two-dimensional feature representation that represents a combination of two features of data. The model learning unit 82 defines a linear model including an inner product of a mapping used in the first kernel function and a first weight and performs learning with the defined linear model. The component expanding unit 83 expands the learned linear model to define expanded component representation that is new component representation of the data. The expansion model generation unit 84 generates an expansion model including an inner product of data by the expanded component representation and a second weight.

2. 发明授权

US11378997B2 Variable phase and frequency pulse-width modulation technique 有权
公开(公告)号：US11378997B2
公开(公告)日：2022-07-05
申请号：US16600496
申请日：2019-10-12
申请人： ULTRAHAPTICS IP LTD
发明人： Benjamin John Oliver Long , Rafel Jibry
IPC分类号： G06F1/025 , G06F17/17
摘要： Phased array systems rely on the production of an exact carrier frequency to function. Reconstructing digital signals by specified amplitude and phase is accomplished explicitly by inducing frequency shifts away from a base frequency implied by phase changes. Shifting the carrier frequency of a digitally controlled phased array while preserving the timing of the individual phase pulses enables more efficient driving of the phased array system when the phase of the drive signals change dynamically in time.

3. 发明申请

US20190242934A1 CALCULATING A LOAD RESISTANCE 审中-公开
公开(公告)号：US20190242934A1
公开(公告)日：2019-08-08
申请号：US15891272
申请日：2018-02-07
申请人： Rockwell Automation Technologies, Inc.
发明人： David Leggate , Russel J. Kerkman , Brian J. Seibel
IPC分类号： G01R27/08 , H03K7/08 , G06F1/025 , H02M7/5387
摘要： For calculating load resistance, a pulse generation module drives a pulse width modulation (PWM) inverter in response to a control voltage. The PWM inverter includes a U phase pole, a V phase pole, and a W phase pole. Each U, V, and W phase pole includes an upper pole device and a lower pole device. The PWM inverter turns off the U phase pole, turns on the W upper pole device, turns off the W lower pole device, and applies the control voltage to the V upper pole device and the V lower pole device. A forward drop correction module corrects the control voltage based on a feedforward compensation voltage determined from a forward voltage drop. A load resistance module calculates a load resistance for a load based on an average control voltage, an average bus voltage, and an average load feedback current.

4. 发明授权

US10270585B2 Clock synchronizer and method of establishing an output clock 有权
公开(公告)号：US10270585B2
公开(公告)日：2019-04-23
申请号：US15698465
申请日：2017-09-07
申请人： Christopher Julian Travis
发明人： Christopher Julian Travis
IPC分类号： H03L7/083 , H03L7/23 , H04L7/033 , G06F1/025 , H03L7/07 , H03L7/085 , H03L7/087 , H03L7/099 , H03K3/03 , H03L7/10
摘要： A hybrid numeric-analog clock synchronizer for establishing a clock or carrier locked to a frequency reference. The clock synchronizer is typically a clock multiplier and a jitter attenuator. The reference may have a low update rate. The synchronizer achieves high jitter rejection, low phase noise and wide frequency range. It can be integrated on chip.

5. 发明授权

US09768949B2 Method of establishing an oscillator clock signal 有权
公开(公告)号：US09768949B2
公开(公告)日：2017-09-19
申请号：US15205126
申请日：2016-07-08
申请人： Christopher Julian Travis
发明人： Christopher Julian Travis
IPC分类号： H03L7/083 , H03L7/23 , H04L7/033 , G06F1/025 , H03L7/07 , H03L7/085 , H03L7/087 , H03L7/099 , H03K3/03 , H03L7/10
CPC分类号： H04L7/0331 , G06F1/025 , G06F2211/902 , H03K3/0307 , H03L7/07 , H03L7/083 , H03L7/085 , H03L7/087 , H03L7/0991 , H03L7/0994 , H03L7/0995 , H03L7/10 , H03L7/235
摘要： A hybrid numeric-analog clock synchronizer, for establishing a clock or carrier locked to a timing reference. The clock may include a framing component. The reference may have a low update rate. The synchronizer achieves high jitter rejection, low phase noise and wide frequency range. It can be integrated on chip. It may comprise a numeric time-locked loop (TLL) with an analog phase-locked loop (PLL). Moreover a high-performance number-controlled oscillator (NCO), for creating an event clock from a master clock according to a period control signal. It processes edge times rather than period values, allowing direct control of the spectrum and peak amplitude of the justification jitter. Moreover a combined clock-and-frame asynchrony detector, for measuring the phase or time offset between composite signals. It responds e.g. to event clocks and frame syncs, enabling frame locking with loop bandwidths greater than the frame rate.

6. 发明授权

US06904471B2 Programmable logic controller customized function call method, system and apparatus 有权
标题翻译：可编程逻辑控制器定制功能调用方法，系统和设备
公开(公告)号：US06904471B2
公开(公告)日：2005-06-07
申请号：US09732574
申请日：2000-12-08
申请人： Mark Steven Boggs , Temple L. Fulton , Steve Hausman , Gary McNabb , Alan McNutt , Steven W. Stimmel
发明人： Mark Steven Boggs , Temple L. Fulton , Steve Hausman , Gary McNabb , Alan McNutt , Steven W. Stimmel
IPC分类号： G06F1/025 , G06F11/36 , H04L1/00 , G06F3/00
CPC分类号： G06F11/3636 , G05B19/056 , G06F1/025
摘要： A programmable logic controller with enhanced and extended the capabilities. A digital input filter implement filters with considerable less logic by simulating the action of a capacitor being driven by a constant current source whose output voltage is sensed by a comparator with a large amount of hysteresis. A pulse catch circuit captures the input pulse even though the update occurs between scan cycles. A pulse output controller includes a hardware pipeline mechanism to allow for smooth, hardware-controlled transitions from wave-form to wave-form. A free port link allows the user to control the port either manually or by operation of a user program. In order to provide higher performance for communication using PPI protocol, the PLC includes a built-in protocol. An n-bit modem protocol ensures data integrity without use of a parity type data integrity system. A hide instruction protects proprietary software by encrypting the sensitive code and decrypting the code during compilation and, thereafter, re-encrypting the code. A system function call allows the user to create and/or download new PLC functions and implement them as PLC operating system functions. An STL status function debugs programs during run-time and while the program is executing. A micro PLC arrangement provides compact size and efficiency.
摘要翻译：可编程逻辑控制器，具有增强和扩展能力。数字输入滤波器通过模拟由恒定电流源驱动的电容器的作用来实现具有相当少的逻辑的滤波器，其输出电压由具有大量滞后的比较器感测。即使在扫描周期之间进行更新，脉冲捕捉电路捕获输入脉冲。脉冲输出控制器包括硬件流水线机制，以允许从波形到波形的平滑的，硬件控制的转换。自由端口链接允许用户手动或通过用户程序的操作来控制端口。为了提供使用PPI协议的通信的更高性能，PLC包括内置协议。 n位调制解调器协议确保数据完整性，而不使用奇偶校验类型数据完整性系统。隐藏指令通过加密敏感代码并在编译期间解密代码，然后重新加密代码来保护专有软件。系统功能调用允许用户创建和/或下载新的PLC功能，并将其实现为PLC操作系统功能。 STL状态功能在运行时和程序执行期间调试程序。微型PLC布局提供了紧凑的尺寸和效率。

7. 发明授权

US06864715B1 Windowing circuit for aligning data and clock signals 有权
标题翻译：用于对准数据和时钟信号的窗口电路
公开(公告)号：US06864715B1
公开(公告)日：2005-03-08
申请号：US10377461
申请日：2003-02-27
申请人： Trevor J. Bauer , Steven P. Young , Christopher D. Ebeling , Jason R. Bergendahl , Arthur J. Behiel
发明人： Trevor J. Bauer , Steven P. Young , Christopher D. Ebeling , Jason R. Bergendahl , Arthur J. Behiel
IPC分类号： G06F1/025 , H03K5/135 , H03K19/177 , H04L7/00 , G06F7/38 , H03D3/24 , H03K19/173
CPC分类号： H03K19/17764 , G06F1/025 , H03K5/135 , H03K19/1774 , H04L7/0004 , H04L7/0037 , H04L7/0041
摘要： Described are circuits and methods for aligning data and clock signals. Circuits in accordance with some embodiments separate incoming data into three differently timed data signals: an early signal, an intermediate signal, and a late signal. The timing of the three data signals can be collectively moved with respect to the clock signal. In addition, the temporal spacing between the three signals can be adjusted so that the early and late signals define a window encompassing the intermediate signal. The three signals are aligned with respect to the clock edge to center the intermediate data signal on the clock edge. The early and late signals can be monitored to identify changes in the relative timing of the clock and data signals. Some embodiments automatically alter the timing of the data and/or clock signals to keep the intermediate data signal centered on the clock edge.
摘要翻译：描述了用于对准数据和时钟信号的电路和方法。根据一些实施例的电路将输入数据分成三个不同定时的数据信号：早期信号，中间信号和后期信号。三个数据信号的定时可以相对于时钟信号共同移动。此外，可以调整三个信号之间的时间间隔，使得早期和晚期信号限定包围中间信号的窗口。三个信号相对于时钟边沿对齐，以使中间数据信号在时钟边沿居中。可以监视早期和晚期信号以识别时钟和数据信号的相对时序的变化。一些实施例自动改变数据和/或时钟信号的定时，以使中间数据信号以时钟边缘为中心。

8. 发明授权

US6150969A Correction of nonlinear output distortion in a Delta Sigma DAC 有权
标题翻译： Delta Sigma DAC中非线性输出失真的校正
公开(公告)号：US6150969A
公开(公告)日：2000-11-21
申请号：US163235
申请日：1998-09-29
申请人： John Laurence Melanson
发明人： John Laurence Melanson
IPC分类号： G06F1/025 , H03M3/04 , H03M7/36 , H03M3/00
CPC分类号： G06F1/025 , H03M3/388 , H03M7/304 , H03M3/506 , H03M7/3026
摘要： A delta sigma modulator of at least second order includes correction means applied to each feedback loop in the modulator, to account for systemic nonlinear output distortions. Since the output distortion is nonlinear, the correction applied to each feedback loop is nontrivially different. Such a corrected delta sigma modulator may be used in a demodulator including an output digital to analog converter (DAC) to account for systemic imperfections in the pulses formed by the DAC. The corrected delta sigma modulator is also useful in correcting output errors associated with high quality multilevel demodulators and class D power amplifiers. The corrected delta sigma modulator may be one bit or multilevel.
摘要翻译：至少二阶的ΔΣ调制器包括施加到调制器中的每个反馈回路的校正装置，以解决系统非线性输出失真。由于输出失真是非线性的，所以施加到每个反馈回路的校正是非常不同的。这种校正的Δ-Σ调制器可以用在包括输出数模转换器（DAC）的解调器中，以解决由DAC形成的脉冲中的系统缺陷。校正的Δ-Σ调制器也可用于校正与高质量多电平解调器和D类功率放大器相关联的输出误差。校正的Δ-Σ调制器可以是一位或多级。

9. 发明授权

US06031401A Clock waveform synthesizer 失效
标题翻译：时钟波形合成器
公开(公告)号：US06031401A
公开(公告)日：2000-02-29
申请号：US92581
申请日：1998-06-08
申请人： Uday Dasgupta
发明人： Uday Dasgupta
IPC分类号： G06F1/025 , G06F1/08 , H03K5/00 , H03K5/156 , H03K3/017
CPC分类号： H03K5/156 , G06F1/025 , G06F1/08 , H03K5/00006
摘要： A clock waveform synthesizer that will create a timing signal that is a multiple of the frequency of an master clock is disclosed and has the capability to programmably adjust the rising edges and falling edges of the synthesized waveform within the period of the master clocks. The clock waveform synthesizer has a multi-tapped delay line. The multi-tapped delay line will create replications of the master clock that are incrementally delayed from the master clock to create a plurality of delay signals. A fraction of the plurality of delay signals will be the inputs to each of a plurality of multiplexers. A select port on each of the multiplexers will receive a select signal to choose one delay signal of the fraction of the plurality of delay signals. The one selected delay signals will be the input to the set terminals and reset terminals of a plurality of edge-triggered set/reset flip-flops. The edge-triggered set/reset flip-flop has an output terminal which will transit from a first logic level to a second logic level when the one selected delay signals is received at the set terminal and will transit from the second logic level to the first logic level when the one selected delay signal is received at the reset terminal. The outputs of the plurality of edge-triggered set/reset flip-flops are connected to the inputs of a combining logic gate, which will combine the signals at the outputs of the edge-triggered set/reset flip-flops to form the synthesized timing signal.
摘要翻译：公开了一种时钟波形合成器，其将产生作为主时钟频率的倍数的定时信号，并且具有在主时钟周期内可编程地调整合成波形的上升沿和下降沿的能力。时钟波形合成器具有多抽头延迟线。多抽头延迟线将产生从主时钟递增延迟的主时钟的复制以产生多个延迟信号。多个延迟信号中的一部分将是多个多路复用器中的每一个的输入。每个复用器上的选择端口将接收选择信号以选择多个延迟信号的一部分的一个延迟信号。一个选择的延迟信号将是多个边沿触发的设置/复位触发器的设置端子和复位端子的输入。边沿触发的设置/复位触发器具有输出端子，当在所设置的端子处接收到一个所选择的延迟信号并且将从第二逻辑电平转移到第一逻辑电平时，该输出端将从第一逻辑电平转换到第二逻辑电平在复位端接收一个所选择的延迟信号时的逻辑电平。多个边沿触发的设置/复位触发器的输出连接到组合逻辑门的输入端，组合逻辑门将组合边沿触发的设置/复位触发器的输出处的信号以形成合成时序信号。

10. 发明授权

US6023741A Pulse width modulation control which data transfer is inhibited by overflow signal 失效
标题翻译：脉冲宽度调制控制哪个数据传输被溢出信号所禁止
公开(公告)号：US6023741A
公开(公告)日：2000-02-08
申请号：US20596
申请日：1998-02-04
申请人： Masaki Yoshino
发明人： Masaki Yoshino
IPC分类号： G01R5/16 , G05B9/02 , G05B11/28 , G06F1/025 , G06F13/00 , H02M7/48 , H02P27/08 , H03K3/72 , H03K7/08 , H04Q9/00 , H03K3/017
CPC分类号： G06F1/025 , H03K7/08
摘要： In a pulse width modulation (PWM) control circuit, a free run counter counts a pulse signal to count a value, and generates an overflow signal when the counted value is equal to a predetermined value. A transfer control circuit allows a set value to be transferred from a master compare register to a slave compare register and inhibits the transfer of the set value in response to the overflow signal. A comparing circuit compares the counted value in the free run counter and the set value transferred into the slave compare register and generates a coincident signal when the counted value is coincident with the set value. An output circuit generates a PWM signal in response to the overflow signal and the coincident signal.
摘要翻译：在脉冲宽度调制（PWM）控制电路中，自由运行计数器对脉冲信号进行计数以计数一个值，并且当计数值等于预定值时产生溢出信号。传输控制电路允许将设定值从主比较寄存器传送到从比较寄存器，并根据溢出信号禁止传送设定值。比较电路将自由运行计数器中的计数值与传送到从比较寄存器的设定值进行比较，当计数值与设定值一致时，产生一致信号。输出电路响应于溢出信号和重合信号产生PWM信号。

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