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1. 发明授权

US09703914B2 Optimizing placement of circuit resources using a globally accessible placement memory 有权
公开(公告)号：US09703914B2
公开(公告)日：2017-07-11
申请号：US15187856
申请日：2016-06-21
申请人： International Business Machines Corporation
发明人： David J. Hathaway , Nathaniel D. Hieter , Shyam Ramji , Alexander J. Suess
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022 , G06F17/5072 , G06F2217/04
摘要： A method, executed by one or more processors, for optimizing placement of a logic network, includes partitioning a logic network into a set of logic partitions, launching a set of placement optimization threads that correspond to the logic partitions, and allocating memory that is accessible to the placement optimization threads to provide a globally accessible placement memory for reserving placement locations on the integrated circuit. Each placement optimization thread may be configured to conduct the operations of determining a desired location for a logic element, reserving a set of potential locations for the logic element, determining a best location from the set of potential locations, and placing the logic element to the best location. Each placement optimization thread may also be configured to release each of the potential locations that are not the best location. A corresponding computer program product and computer system are also disclosed herein.

2. 发明授权

US09639654B2 Managing virtual boundaries to enable lock-free concurrent region optimization of an integrated circuit 有权
公开(公告)号：US09639654B2
公开(公告)日：2017-05-02
申请号：US14567569
申请日：2014-12-11
申请人： International Business Machines Corporation
发明人： Bijian Chen , David J. Hathaway , Nathaniel D. Hieter , Kerim Kalafala , Jeffrey S. Piaget , Alexander J. Suess
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/505 , G06F17/5068 , G06F2217/04
摘要： Managing virtual boundaries to enable lock-free concurrent region optimization, including: receiving a model of an integrated circuit (‘IC’); dividing the model into a plurality of regions, wherein none of the plurality of regions overlap with another region; assigning each of the plurality of regions to a thread of execution, wherein each thread of execution utilizes a shared memory space; and optimizing, by each thread in parallel, the assigned region.

3. 发明申请

US20170083642A1 OPTIMIZING PLACEMENT OF CIRCUIT RESOURCES USING A GLOBALLY ACCESSIBLE PLACEMENT MEMORY 有权
公开(公告)号：US20170083642A1
公开(公告)日：2017-03-23
申请号：US15371251
申请日：2016-12-07
申请人： International Business Machines Corporation
发明人： David J. Hathaway , Nathaniel D. Hieter , Shyam Ramji , Alexander J. Suess
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022 , G06F17/5072 , G06F2217/04
摘要： A method, executed by one or more processors, for optimizing placement of a logic network, includes partitioning a logic network into a set of logic partitions, launching a set of placement optimization threads that correspond to the logic partitions, and allocating memory that is accessible to the placement optimization threads to provide a globally accessible placement memory for reserving placement locations on the integrated circuit. Each placement optimization thread may be configured to conduct the operations of determining a desired location for a logic element, reserving a set of potential locations for the logic element, determining a best location from the set of potential locations, and placing the logic element to the best location. Each placement optimization thread may also be configured to release each of the potential locations that are not the best location. A corresponding computer program product and computer system are also disclosed herein.

4. 发明申请

US20160253214A1 EFFICIENT PARALLEL PROCESSING OF A NETWORK WITH CONFLICT CONSTRAINTS BETWEEN NODES 有权
标题翻译：网络的有效并发处理与NODES之间的冲突约束
公开(公告)号：US20160253214A1
公开(公告)日：2016-09-01
申请号：US15045727
申请日：2016-02-17
申请人： International Business Machines Corporation
发明人： Hemlata Gupta , David J. Hathaway , Kerim Kalafala , Ronald D. Rose
IPC分类号： G06F9/50
CPC分类号： H04L41/14 , G06F9/5038 , G06F9/5066 , G06F9/5083 , H04L41/5003 , H04L43/08 , H04L47/125 , H04L67/10
摘要： According to one exemplary embodiment, a method for parallel processing a network of nodes having at least one ordering constraint and at least one conflict constraint is provided. The method may include breaking a plurality of loops caused by the at least one ordering constraint. The method may also include determining a node order based on the at least one ordering constraint. The method may then include determining a conflict order based on the at least one conflict constraint, whereby no new loops are created in the network. The method may further include performing parallel processing of the network of nodes based on the node order and the conflict order.
摘要翻译：根据一个示例性实施例，提供了一种用于并行处理具有至少一个排序约束和至少一个冲突约束的节点网络的方法。该方法可以包括中断由至少一个排序约束引起的多个循环。该方法还可以包括基于至少一个排序约束来确定节点顺序。该方法然后可以包括基于至少一个冲突约束来确定冲突顺序，由此在网络中不创建新的循环。该方法还可以包括基于节点顺序和冲突顺序执行节点网络的并行处理。

5. 发明授权

US09262569B2 Balancing sensitivities with respect to timing closure for integrated circuits 有权
标题翻译：平衡集成电路时序闭合的灵敏度
公开(公告)号：US09262569B2
公开(公告)日：2016-02-16
申请号：US14185079
申请日：2014-02-20
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Jeanne P. Bickford , Eric A. Foreman , David J. Hathaway
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/84
摘要： Systems and methods for improving timing closure of new and existing semiconductor products by balancing sensitivities. More specifically, a method is provided for that includes defining at least one set of correlated parameters for a semiconductor product, the at least one set of correlated parameters comprising a first parameter and a second parameter. The method further includes measuring performance of embedded devices within the semiconductor product. The method further includes closing timing of the semiconductor product using the measured performance of the semiconductor product. The closing the timing of the semiconductor product comprises calculating a sensitivity to the first parameter based on the measured performance of the embedded devices within the semiconductor product and balancing the sensitivity to the first parameter with a sensitivity to a second parameter such that timing degradation is shifted from the first parameter to the second parameter.
摘要翻译：通过平衡灵敏度来改善新的和现有的半导体产品的时序关闭的系统和方法。更具体地，提供了一种方法，其包括为半导体产品定义至少一组相关参数，所述至少一组相关参数包括第一参数和第二参数。该方法还包括测量半导体产品内的嵌入式设备的性能。该方法还包括使用所测量的半导体产品的性能来关闭半导体产品的定时。关闭半导体产品的定时包括基于半导体产品内的嵌入式设备的测量性能来计算对第一参数的灵敏度，并且以对第二参数的灵敏度平衡与第一参数的灵敏度，使得定时劣化被移位从第一个参数到第二个参数。

6. 发明授权

US08949765B2 Modeling multi-patterning variability with statistical timing 有权
标题翻译：用统计时序建模多图案变异
公开(公告)号：US08949765B2
公开(公告)日：2015-02-03
申请号：US14139004
申请日：2013-12-23
申请人： International Business Machines Corporation
发明人： Nathan Buck , Brian Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5072 , G06F2217/08 , G06F2217/10 , G06F2217/12 , G06F2217/84
摘要： Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to define at least one source of variation in an integrated circuit design. The programming instructions further operable to model the at least one source of variation for at least two patterns in at least one level of the integrated circuit design as at least two sources of variability respectively.
摘要翻译：描述了在IC制造期间利用统计时序分析建模多图案变化的系统和方法。该方法可以被提供在具有计算机可执行代码的计算机基础结构中，计算机可执行代码有形地体现在具有可编程指令的计算机可读存储介质上，该程序指令可操作以限定集成电路设计中的至少所述编程指令进一步可操作以将集成电路设计的至少一个级别中的至少两个模式的所述至少一个变化源建模为至少两个变异性源。

7. 发明申请

US20140375380A1 OPTIMIZING OPERATING RANGE OF AN ELECTRONIC CIRCUIT 有权
标题翻译：优化电子电路的运行范围
公开(公告)号：US20140375380A1
公开(公告)日：2014-12-25
申请号：US13921784
申请日：2013-06-19
申请人： International Business Machines Corporation
发明人： John M. Cohn , David J. Hathaway , Sridhar H. Rangarajan , Diyanesh Babu C. Vidyapoornachary
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/505 , G06F17/5068 , G06F17/5081 , G06F2217/78 , G06F2217/84
摘要： According to a method herein, a portion of an electronic circuit is identified. The electronic circuit comprises logic circuitry. The portion of the electronic circuit is designed in at least two versions. Each of the at least two versions is evaluated using a plurality of operating conditions. The current operating conditions are determined. One version of the at least two versions is identified as a selected version based on the performance under the current operating conditions. The selected version has relatively optimal performance based on at least one of clock frequency, supply voltage, and power limit. The selected version is activated for use in the portion of the electronic circuit. The remaining versions of the at least two versions are deactivated.
摘要翻译：根据本文的方法，识别电子电路的一部分。电子电路包括逻辑电路。电子电路的部分设计为至少两个版本。使用多个操作条件来评估至少两个版本中的每一个。确定当前的操作条件。基于当前操作条件下的性能，将至少两个版本的一个版本识别为选定的版本。所选版本基于时钟频率，电源电压和功率限制中的至少一个具有相对最佳的性能。所选版本被激活以用于电子电路的该部分。至少两个版本的剩余版本被停用。

8. 发明授权

US08832625B2 Systems and methods for correlated parameters in statistical static timing analysis 有权
公开(公告)号：US08832625B2
公开(公告)日：2014-09-09
申请号：US13780413
申请日：2013-02-28
申请人： International Business Machines Corporation
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031 , G06F17/5081
摘要： Systems and methods for accommodating correlated parameters in SSTA are provided. The method includes determining a correlation between at least two parameters. The method further includes calculating a new parameter or a new parameter set based on the correlation between the at least two parameters. The method further includes performing the SSTA such that the new parameter or the new parameter set is propagated into the SSTA. The method further includes projecting slack using the correlation between the at least two parameters and using a processor.

9. 发明授权

US09852246B2 System and method for efficient statistical timing analysis of cycle time independent tests 有权
公开(公告)号：US09852246B2
公开(公告)日：2017-12-26
申请号：US14955231
申请日：2015-12-01
申请人： International Business Machines Corporation
发明人： David J. Hathaway , Kerim Kalafala , Stephen G. Shuma , Chandramouli Visweswariah
IPC分类号： G06F11/22 , G06F17/50
CPC分类号： G06F17/5045 , G06F17/5031 , G06F2217/84
摘要： A system performing selected timing comparisons in a digital electronic design includes propagating from signal sources to timing comparisons of one or multiple signal labels. The signal label includes signal source identifiers and signal path cycle adjust information. Timing comparisons are determined in which signal label values at each input of the timing comparison are required to compute the selected timing comparisons. The propagation back from the timing comparisons are needed signal labels, followed by the propagation and computing timing data from the signal source applied to the propagated signal labels corresponding to the required signal labels.

10. 发明申请

US20170111232A1 EFFICIENT PARALLEL PROCESSING OF A NETWORK WITH CONFLICT CONSTRAINTS BETWEEN NODES 有权
公开(公告)号：US20170111232A1
公开(公告)日：2017-04-20
申请号：US15402596
申请日：2017-01-10
申请人： International Business Machines Corporation
发明人： Hemlata Gupta , David J. Hathaway , Kerim Kalafala , Ronald D. Rose
IPC分类号： H04L12/24 , H04L29/08 , H04L12/803 , H04L12/26
CPC分类号： H04L41/14 , G06F9/5038 , G06F9/5066 , G06F9/5083 , H04L41/5003 , H04L43/08 , H04L47/125 , H04L67/10
摘要： According to one exemplary embodiment, a method for parallel processing a network of nodes having at least one ordering constraint and at least one conflict constraint is provided. The method may include breaking a plurality of loops caused by the at least one ordering constraint. The method may also include determining a node order based on the at least one ordering constraint. The method may then include determining a conflict order based on the at least one conflict constraint, whereby no new loops are created in the network. The method may further include performing parallel processing of the network of nodes based on the node order and the conflict order.

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