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1. 发明授权

US10794948B2 Electromigration monitor 有权
公开(公告)号：US10794948B2
公开(公告)日：2020-10-06
申请号：US15805377
申请日：2017-11-07
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Fen Chen , Mukta G. Farooq , John A. Griesemer , Chandrasekaran Kothandaraman , John M. Safran , Timothy D. Sullivan , Ping-Chuan Wang , Lijuan Zhang
IPC分类号： H01L21/66 , G01R31/08 , H01L23/48 , G01R31/28
摘要： An EM testing method includes forcing electrical current through EM monitor wiring arranged in close proximity to the perimeter of the TSV and measuring an electrical resistance drop across the EM monitor wiring. The method may further include determining if an electrical short exists between the EM monitor wiring and the TSV from the measured electrical resistance. The method may further include determining if an early electrical open or resistance increase exists within the EM monitoring wiring due to TSV induced proximity effect.

2. 发明授权

US09985615B2 On-chip randomness generation 有权
公开(公告)号：US09985615B2
公开(公告)日：2018-05-29
申请号：US15421465
申请日：2017-02-01
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Kai D. Feng , Ping-Chuan Wang , Zhijian Yang , Emmanuel Yashchin
IPC分类号： H03K3/84 , H03K5/01 , H03K3/012
CPC分类号： H03K3/84 , H03K3/012 , H03K3/313 , H03K5/01
摘要： An on-chip true noise generator including an embedded noise source with a low-voltage, high-noise zener diode(s), and an in-situ close-loop zener diode power control circuit. The present invention proposes the use of heavily doped polysilicon and silicon p-n diode(s) structures to minimize the breakdown voltage, increasing noise level and improving reliability. The present invention also proposes an in-situ close-loop zener diode control circuit to safe-guard the zener diode from catastrophic burn-out.

3. 发明申请

US20180074111A1 ELECTROMIGRATION MONITOR 审中-公开
公开(公告)号：US20180074111A1
公开(公告)日：2018-03-15
申请号：US15805406
申请日：2017-11-07
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Fen Chen , Mukta G. Farooq , John A. Griesemer , Chandrasekaran Kothandaraman , John M. Safran , Timothy D. Sullivan , Ping-Chuan Wang , Lijuan Zhang
IPC分类号： G01R31/08 , H01L21/66 , H01L23/48
CPC分类号： G01R31/08 , G01R31/2856 , G01R31/2858 , H01L22/14 , H01L22/34 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A structure, such as a wafer, semiconductor chip, integrated circuit, or the like, includes a through silicon via (TSV) and an electromigration (EM) monitor. The TSV) incldues at least one perimeter sidewall. The EM monitor includes a first EM wire separated from the perimeter sidewall of the TSV by a dielectric

4. 发明申请

US20180005961A1 WAFER REINFORCEMENT TO REDUCE WAFER CURVATURE 审中-公开
公开(公告)号：US20180005961A1
公开(公告)日：2018-01-04
申请号：US15707504
申请日：2017-09-18
申请人： International Business Machines Corporation
发明人： Erdem Kaltalioglu , Andrew T. Kim , Chengwen Pei , Ping-Chuan Wang
IPC分类号： H01L23/00 , H01L21/762 , H01L21/308 , H01L21/3105 , H01L29/66 , H01L29/06
CPC分类号： H01L23/562 , H01L21/308 , H01L21/31051 , H01L21/76283 , H01L29/0649 , H01L29/66795
摘要： A semiconductor structure includes filled dual reinforcing trenches that reduce curvature of the semiconductor structure by stiffening the semiconductor structure. The filled dual reinforcing trenches reduce curvature by acting against transverse loading, axial loading, and/or torsional loading of the semiconductor structure that would otherwise result in semiconductor structure curvature. The filled dual reinforcing trenches may be located in an array throughout the semiconductor structure, in particular locations within the semiconductor structure, or at the perimeter of the semiconductor structure.

5. 发明授权

US09761539B2 Wafer rigidity with reinforcement structure 有权
公开(公告)号：US09761539B2
公开(公告)日：2017-09-12
申请号：US14753768
申请日：2015-06-29
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Ronald G. Filippi , Erdem Kaltalioglu , Andrew T. Kim , Ping-Chuan Wang
IPC分类号： H01L23/48 , H01L23/00 , H01L21/768
CPC分类号： H01L23/562 , H01L21/76868 , H01L21/76898 , H01L23/481
摘要： Reinforcement structures used with a thinned wafer and methods of manufacture are provided. The method includes forming trenches or vias at least partially through a backside of a thinned wafer attached to a carrier wafer. The method further includes depositing material within the trenches or vias to form reinforcement structures on the backside of the thinned wafer. The method further includes removing excess material from a surface of the thinned wafer, which was deposited during the depositing of the material within the vias.

6. 发明申请

US20160247770A1 ON-CHIP SEMICONDUCTOR DEVICE HAVING ENHANCED VARIABILITY 有权
标题翻译：具有增强可变性的片上半导体器件
公开(公告)号：US20160247770A1
公开(公告)日：2016-08-25
申请号：US15080650
申请日：2016-03-25
申请人： International Business Machines Corporation
发明人： Wai-Kin Li , Chengwen Pei , Ping-Chuan Wang
IPC分类号： H01L23/00 , H01L29/423 , H01L27/02
CPC分类号： H01L23/576 , H01L21/28158 , H01L21/823462 , H01L23/573 , H01L27/0207 , H01L27/088 , H01L29/42368 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A physical unclonable function (PUF) semiconductor device includes a semiconductor substrate extending along a first direction to define a length and a second direction opposite the first direction to define a thickness. At least one pair of semiconductor structures is formed on the semiconductor substrate. The semiconductor structures include a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first gate dielectric layer having a first shape that defines a first threshold voltage. The second semiconductor structure includes a second gate dielectric layer having a second dielectric shape that is reversely arranged with respect to the first shape and that defines a second threshold voltage different from the first threshold voltage.
摘要翻译：物理不可克隆功能（PUF）半导体器件包括沿着第一方向延伸以限定长度的半导体衬底和与第一方向相反的第二方向以限定厚度。在半导体衬底上形成至少一对半导体结构。半导体结构包括第一半导体结构和第二半导体结构。第一半导体结构包括具有限定第一阈值电压的第一形状的第一栅极电介质层。第二半导体结构包括具有第二电介质形状的第二栅介质层，其相对于第一形状相反地布置并且限定不同于第一阈值电压的第二阈值电压。

7. 发明授权

US09391030B1 On-chip semiconductor device having enhanced variability 有权
标题翻译：具有增强的变化性的片上半导体器件
公开(公告)号：US09391030B1
公开(公告)日：2016-07-12
申请号：US14625943
申请日：2015-02-19
申请人： International Business machines Corporation
发明人： Wai-Kin Li , Chengwen Pei , Ping-Chuan Wang
IPC分类号： H01L21/302 , H01L23/00 , H01L27/088 , H01L29/423 , H01L21/8236 , H01L21/28
CPC分类号： H01L23/576 , H01L21/28158 , H01L21/823462 , H01L23/573 , H01L27/0207 , H01L27/088 , H01L29/42368 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A physical unclonable function (PUF) semiconductor device includes a semiconductor substrate extending along a first direction to define a length and a second direction opposite the first direction to define a thickness. At least one pair of semiconductor structures is formed on the semiconductor substrate. The semiconductor structures include a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first gate dielectric layer having a first shape that defines a first threshold voltage. The second semiconductor structure includes a second gate dielectric layer having a second dielectric shape that is reversely arranged with respect to the first shape and that defines a second threshold voltage different from the first threshold voltage.
摘要翻译：物理不可克隆功能（PUF）半导体器件包括沿着第一方向延伸以限定长度的半导体衬底和与第一方向相反的第二方向以限定厚度。在半导体衬底上形成至少一对半导体结构。半导体结构包括第一半导体结构和第二半导体结构。第一半导体结构包括具有限定第一阈值电压的第一形状的第一栅极电介质层。第二半导体结构包括具有第二电介质形状的第二栅介质层，其相对于第一形状相反地布置并且限定不同于第一阈值电压的第二阈值电压。

8. 发明授权

US09305879B2 E-fuse with hybrid metallization 有权
标题翻译：电子熔断器采用混合金属化
公开(公告)号：US09305879B2
公开(公告)日：2016-04-05
申请号：US14024694
申请日：2013-09-12
申请人： International Business Machines Corporation
发明人： Ronald G. Filippi , Erdem Kaltalioglu , Andrew T. Kim , Ping-Chuan Wang , Lijuan Zhang
IPC分类号： H01L23/525 , H01L21/768 , H01L23/532
CPC分类号： H01L23/5256 , H01L21/76886 , H01L23/53266 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An e-fuse structure including a fuse link having a first region made of a first conductor and a second region made of a second conductor. The first conductor and the second conductor are in the same wiring level. The first conductor has a higher electrical resistance than the second conductor. The first conductor has a higher resistance to electromigration than the second conductor. The first region and the second region have a common width. The length of the first region is longer than the length of the second region.
摘要翻译：一种电熔丝结构，包括具有由第一导体制成的第一区域和由第二导体制成的第二区域的熔丝连接。第一导体和第二导体处于相同的布线层。第一导体具有比第二导体更高的电阻。第一导体比第二导体具有更高的电迁移阻力。第一区域和第二区域具有共同的宽度。第一区域的长度比第二区域的长度长。

9. 发明授权

US09189654B2 On-chip structure for security application 有权
标题翻译：用于安全应用的片上结构
公开(公告)号：US09189654B2
公开(公告)日：2015-11-17
申请号：US14096345
申请日：2013-12-04
申请人： International Business Machines Corporation
发明人： Kai Di Feng , Wai-Kin Li , Chengwen Pei , Ping-Chuan Wang
IPC分类号： G06F21/71 , G06F7/58
CPC分类号： G06F21/71 , G06F7/588 , G06F21/73
摘要： A set of physical unclonable function (PUF) cells is configured with a set of capacitive devices in an integrated circuit (IC). A subset of PUF cells includes a corresponding subset of capacitive devices that have failed during fabrication. A charging current sufficient to charge an operational capacitive device in a PUF cell is sent to the set of PUF cells. A determination is made whether an output voltage of a PUF cell exceeds a threshold. When the output voltage exceeding the threshold, a logic value of 1 is produced at a position in a bit-string. The determination and the producing is repeated for each PUF cell in the set to output a bit-string, which includes 1s and 0s in random positions. The bit-string is used in a security application as a random stable value owing to a random pattern of 1s and 0s present in the bit-string.
摘要翻译：一组物理不可克隆功能（PUF）单元在集成电路（IC）中配置有一组电容性器件。 PUF单元的子集包括在制造期间失败的电容器件的相应子集。向PUF单元中的操作电容性装置充电的充电电流被发送到PUF单元组。确定PUF单元的输出电压是否超过阈值。当输出电压超过阈值时，在位串中的位置产生逻辑值1。对集合中的每个PUF单元重复确定和产生，以输出位串，其包括随机位置中的1和0。由于位串中存在1和0的随机模式，因此位串在安全应用程序中用作随机稳定值。

10. 发明申请

US20150235964A1 PHOTORESIST COLLAPSE METHOD FOR FORMING A PHYSICAL UNCLONABLE FUNCTION 有权
标题翻译：用于形成物理不可靠函数的光电聚焦方法
公开(公告)号：US20150235964A1
公开(公告)日：2015-08-20
申请号：US14181960
申请日：2014-02-17
申请人： International Business Machines Corporation
发明人： Kai D. Feng , Wai-Kin Li , Ping-Chuan Wang , Zhijian Yang
IPC分类号： H01L23/544 , H01L21/3105
CPC分类号： H01L21/32139 , G09C1/00 , H01L21/0273 , H01L21/31058 , H01L21/31138 , H01L21/31144 , H01L21/76816 , H01L21/76885 , H01L22/34 , H01L23/522 , H01L23/5221 , H01L23/5226 , H01L23/5228 , H01L23/528 , H01L23/5386 , H01L23/544 , H01L23/57 , H01L2223/54433 , H01L2223/5444 , H01L2223/5448 , H01L2224/05097 , H04L9/3278 , H04L2209/12
摘要： An organic material layer is lithographically patterned to include a linear array portion of lines and spaces. In one embodiment, the organic material layer can be an organic planarization layer that is patterned employing a photoresist layer, which is consumed during patterning of the organic planarization layer. Volume expansion of the organic planarization layer upon exposure to a halogen-including gas causes portions of the linear array to collapse at random locations. In another embodiment, the height of the photoresist layer is selected such that the linear array portion of the photoresist layer is mechanically unstable and produces random photoresist collapses. The pattern including random modifications due to the collapse of the organic material layer is transferred into an underlying layer to generate an array of conductive material lines with random electrical disruption of shorts or opens. The structure with random shorts can be employed as a physical unclonable function.
摘要翻译：有机材料层被光刻图案化以包括线和空间的直线阵列部分。在一个实施例中，有机材料层可以是利用在有机平坦化层的图案化期间消耗的光致抗蚀剂层进行图案化的有机平坦化层。有机平面化层在暴露于含卤素气体时的体积膨胀导致线性阵列的部分在随机位置崩溃。在另一个实施方案中，选择光致抗蚀剂层的高度，使得光致抗蚀剂层的线性阵列部分在机械上不稳定并产生随机光刻胶塌陷。由于有机材料层的崩溃引起的包括随机修饰的图案被转移到下层中，以产生具有短路或开放的随机电气中断的导电材料线的阵列。具有随机短路的结构可用作物理不可克隆功能。

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