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1. 发明申请

US20180294213A1 REDUCTION OF STRESS IN VIA STRUCTURE 审中-公开
公开(公告)号：US20180294213A1
公开(公告)日：2018-10-11
申请号：US15480750
申请日：2017-04-06
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Toyohiro Aoki , Takashi Hisada , Akihiro Horibe , Sayuri Hada , Eiji I. Nakamura , Kuniaki Sueoka
IPC分类号： H01L23/498 , H01L23/48 , H01L21/768
CPC分类号： H01L23/49827 , H01L21/76898 , H01L23/481 , H01L2924/00014 , H01L2924/0002
摘要： A via structure for electric connection is disclosed. The via structure includes a substrate that has a first surface and a via hole opened to the first surface. The via structure includes also a stress buffer layer disposed on the first surface of the substrate, which has an opening aligned to the via hole of the substrate. The via structure further includes a conductive body formed in the via hole of the substrate at least up to the level of the first surface of the substrate. In the via structure, the stress buffer layer receives the conductive body extending into the opening over the level of the first surface of the substrate and/or covers, at least in part, the edge of the first surface around the via hole of the substrate.

2. 发明授权

US10074583B2 Circuit module and manufacturing method thereof 有权
公开(公告)号：US10074583B2
公开(公告)日：2018-09-11
申请号：US14927989
申请日：2015-10-30
申请人： International Business Machines Corporation
发明人： Akihiro Horibe , Sayuri Hada , Kuniaki Sueoka
IPC分类号： H01L23/31 , H01L23/498 , H01L21/56 , H01L21/683 , H01L21/78 , H01L23/00
CPC分类号： H01L23/3157 , H01L21/561 , H01L21/563 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L23/3178 , H01L23/49811 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/94 , H01L29/0657 , H01L2221/68327 , H01L2221/68381 , H01L2224/16227 , H01L2224/26145 , H01L2224/27002 , H01L2224/27013 , H01L2224/29082 , H01L2224/2929 , H01L2224/29386 , H01L2224/29499 , H01L2224/32225 , H01L2224/73104 , H01L2224/73204 , H01L2224/81191 , H01L2224/81447 , H01L2224/81815 , H01L2224/8185 , H01L2224/83191 , H01L2224/83862 , H01L2224/9211 , H01L2224/94 , H01L2924/10156 , H01L2224/11 , H01L2224/27 , H01L2924/00014
摘要： There is provided a circuit module where a sufficient amount of underfill resin may be supplied to corner portions of a semiconductor chip. A circuit module includes a circuit board provided with a plurality of electrode pads on a surface of the board, a semiconductor chip arranged on the board, the chip including a surface and a back surface, where each of a plurality of solder bumps and provided on the back surface is solder joined to a corresponding one of the plurality of electrode pads, and an underfill provided between the surface of the board and the back surface of the chip. Furthermore, the chip includes an eaves portion of a predetermined thickness at an outer periphery of the surface, and the underfill forms a fillet extending from a bottom surface of the eaves portion to the surface of the board along a side wall of the chip.

3. 发明申请

US20160217247A1 REDUCTION OF WARPAGE OF MULTILAYERED SUBSTRATE OR PACKAGE 有权
标题翻译：减少多层基板或包装的保修
公开(公告)号：US20160217247A1
公开(公告)日：2016-07-28
申请号：US15086984
申请日：2016-03-31
申请人： International Business Machines Corporation
发明人： Sayuri Hada , Keiji Matsumoto
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5018 , G06F17/5068 , G06F17/5077 , G06F17/5086 , G06F2217/12 , Y02P90/265
摘要： A method that minimizes adjustment of a wiring layer in reducing a warpage of a multilayered substrate and enables location of a part of a wiring layer that needs correction in order to reduce the warpage. The difference in average coefficient of thermal expansion, Δα, varies in a substrate. The method focuses in on the difference in Δα with a great length scale (low frequency) having a relatively significant effect on the warpage compared to the difference in Δα with a smaller length scale (high frequency) and corrects only the difference in Δα with a greater length scale. The distribution of the difference in Δα in a plane of substrate is determined. Then digital filtering is performed to extract only the difference in Δα with a low frequency and the difference in Δα between before and after correction, thereby revealing a part that requires correction.
摘要翻译：一种减少布线层的调整以减少多层基板的翘曲的方法，并且能够定位需要校正的布线层的一部分以减少翘曲。平均热膨胀系数Δα的差在基板中变化。该方法集中在与具有较小长度尺度（高频）的Δα的差异相比，具有与翘曲相对显着影响的较大长度尺度（低频）的Δα的差异，并且仅校正Δα的差异更长的刻度。确定基板平面中Δα差异的分布。然后执行数字滤波以仅提取Δα与低频之间的差异以及校正之前和之后Δα的差异，从而显示需要校正的部分。

4. 发明授权

US09672323B2 Reduction of warpage of multilayered substrate or package 有权
公开(公告)号：US09672323B2
公开(公告)日：2017-06-06
申请号：US15086984
申请日：2016-03-31
申请人： International Business Machines Corporation
发明人： Sayuri Hada , Keiji Matsumoto
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5018 , G06F17/5068 , G06F17/5077 , G06F17/5086 , G06F2217/12 , Y02P90/265
摘要： A method that minimizes adjustment of a wiring layer in reducing a warpage of a multilayered substrate and enables location of a part of a wiring layer that needs correction in order to reduce the warpage. The difference in average coefficient of thermal expansion, Δα, varies in a substrate. The method focuses in on the difference in Δα with a great length scale (low frequency) having a relatively significant effect on the warpage compared to the difference in Δα with a smaller length scale (high frequency) and corrects only the difference in Δα with a greater length scale. The distribution of the difference in Δα in a plane of substrate is determined. Then digital filtering is performed to extract only the difference in Δα with a low frequency and the difference in Δα between before and after correction, thereby revealing a part that requires correction.

5. 发明申请

US20170142825A1 METHOD OF REDUCING WARPAGE OF AN ORGACNIC SUBSTRATE 有权
公开(公告)号：US20170142825A1
公开(公告)日：2017-05-18
申请号：US14938917
申请日：2015-11-12
申请人： International Business Machines Corporation
发明人： Sayuri Hada , Hiroyuki Mori , Keishi Okamoto
IPC分类号： H05K1/02 , G01B21/20 , H05K3/22 , G01B21/08 , H05K1/03 , H05K3/00
CPC分类号： H05K1/0271 , G01B21/08 , G01B21/20 , H05K1/0298 , H05K1/0313 , H05K3/0011 , H05K3/225 , H05K3/4644 , H05K2201/09136 , H05K2201/09909 , H05K2203/013 , H05K2203/163
摘要： A method for reducing warpage on an organic substrate. The method includes: preparing an organic substrate, which includes (i) a core layer having an organic material, (ii) a first buildup layer on a front surface of the core layer, and (iii) a second buildup layer on a back surface of the core layer, measuring warpage of the organic substrate, calculating a thickness of a correction layer for reducing the warpage using properties of constituent materials including the coefficient of thermal expansion (CTE) and the Young's modulus of the core layer, and CTEs and the Young's modulus of the first and the second buildup layers, and forming at least one correction layer having the thickness on at least one part of surfaces of the first buildup layer and the second buildup layer. A system and an organic substrate is also provided.

6. 发明授权

US09568405B2 Method, apparatus, and structure for determining interposer thickness 有权
标题翻译：用于确定插层厚度的方法，装置和结构
公开(公告)号：US09568405B2
公开(公告)日：2017-02-14
申请号：US14554088
申请日：2014-11-26
申请人： International Business Machines Corporation
发明人： Sayuri Hada , Akihiro Horibe , Keiji Matsumoto
IPC分类号： G01N3/20 , G01N3/22 , G01L1/26 , G01N25/16
CPC分类号： G01N3/22 , G01L1/26 , G01N3/20 , G01N25/16 , G01N2203/0057
摘要： The present invention includes the following steps: setting the thickness of an interposer to an initial value; determining the axial force of the interposer and the radius of curvature of the warpage caused by the difference in the thermal expansion coefficients of the supporting substrate, the joined layer and the interposer at the set thickness; determining the absolute value of the stress on the chip-connecting surface of the interposer from the stress due to the axial force of the interposer and the stress due to the warpage using the determined axial force and the radius of curvature; determining whether or not the absolute value of the stress is within a tolerance; changing the thickness of the interposer by a predetermined value; and confirming the set thickness as the thickness of the interposer when the determined absolute value of the stress is within the tolerance.
摘要翻译：本发明包括以下步骤：将中介层的厚度设定为初始值; 确定插入件的轴向力和由设定厚度的支撑基板，接合层和插入件的热膨胀系数的差异引起的翘曲的曲率半径; 确定插入件的芯片连接表面上的应力的绝对值与由插入件的轴向力引起的应力和使用所确定的轴向力和曲率半径的翘曲引起的应力; 确定应力的绝对值是否在容差内; 将所述插入件的厚度改变预定值; 并且当确定的应力绝对值在公差内时，将设定厚度确认为中介层的厚度。

7. 发明申请

US20150153406A1 METHOD, APPARATUS, AND STRUCTURE FOR DETERMINING INTERPOSER THICKNESS 有权
标题翻译：方法，装置和结构确定间距厚度
公开(公告)号：US20150153406A1
公开(公告)日：2015-06-04
申请号：US14554088
申请日：2014-11-26
申请人： International Business Machines Corporation
发明人： Sayuri Hada , Akihiro Horibe , Keiji Matsumoto
IPC分类号： G01R31/28 , G01N3/20 , G01N3/22 , G01N25/16
CPC分类号： G01N3/22 , G01L1/26 , G01N3/20 , G01N25/16 , G01N2203/0057
摘要： The present invention includes the following steps: setting the thickness of an interposer to an initial value; determining the axial force of the interposer and the radius of curvature of the warpage caused by the difference in the thermal expansion coefficients of the supporting substrate, the joined layer and the interposer at the set thickness; determining the absolute value of the stress on the chip-connecting surface of the interposer from the stress due to the axial force of the interposer and the stress due to the warpage using the determined axial force and the radius of curvature; determining whether or not the absolute value of the stress is within a tolerance; changing the thickness of the interposer by a predetermined value; and confirming the set thickness as the thickness of the interposer when the determined absolute value of the stress is within the tolerance.
摘要翻译：本发明包括以下步骤：将中介层的厚度设定为初始值; 确定插入件的轴向力和由设定厚度的支撑基板，接合层和插入件的热膨胀系数的差异引起的翘曲的曲率半径; 确定插入件的芯片连接表面上的应力的绝对值与由插入件的轴向力引起的应力和使用所确定的轴向力和曲率半径的翘曲引起的应力; 确定应力的绝对值是否在容差内; 将所述插入件的厚度改变预定值; 并且当确定的应力绝对值在公差内时，将设定厚度确认为中介层的厚度。

8. 发明授权

US10679916B2 Circuit module and manufacturing method thereof 有权
公开(公告)号：US10679916B2
公开(公告)日：2020-06-09
申请号：US16110389
申请日：2018-08-23
申请人： International Business Machines Corporation
发明人： Akihiro Horibe , Sayuri Hada , Kuniaki Sueoka
IPC分类号： H01L23/31 , H01L23/498 , H01L21/56 , H01L21/78 , H01L23/00 , H01L21/683 , H01L29/06
摘要： There is provided a circuit module where a sufficient amount of underfill resin may be supplied to corner portions of a semiconductor chip. A circuit module includes a circuit board provided with a plurality of electrode pads on a surface of the board, a semiconductor chip arranged on the board, the chip including a surface and a back surface, where each of a plurality of solder bumps and provided on the back surface is solder joined to a corresponding one of the plurality of electrode pads, and an underfill provided between the surface of the board and the back surface of the chip. Furthermore, the chip includes an eaves portion of a predetermined thickness at an outer periphery of the surface, and the underfill forms a fillet extending from a bottom surface of the eaves portion to the surface of the board along a side wall of the chip.

9. 发明授权

US10595399B2 Method of reducing warpage of an organic substrate 有权
公开(公告)号：US10595399B2
公开(公告)日：2020-03-17
申请号：US15872009
申请日：2018-01-16
申请人： International Business Machines Corporation
发明人： Sayuri Hada , Hiroyuki Mori , Keishi Okamoto
IPC分类号： B32B3/00 , H05K1/02 , G01B21/08 , G01B21/20 , H05K3/00 , H05K3/22 , H05K1/03 , H05K3/46
摘要： An organic substrate includes a core layer including organic materials; a first buildup layer on a top surface of the core layer; a second buildup layer on a bottom surface of the core layer; and at least one correction layer formed on at least one part of surfaces of the first buildup layer and the second buildup layer, wherein the correction layer has a thickness which has been calculated using properties of constituent materials including the coefficient of thermal expansion (CTE) and the Young's modulus of the core layer, and CTEs and the Young's modulus of the first and the second buildup layers for reducing warpage of the organic substrate.

10. 发明授权

US10325839B2 Reduction of stress in via structure 有权
公开(公告)号：US10325839B2
公开(公告)日：2019-06-18
申请号：US15480750
申请日：2017-04-06
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Toyohiro Aoki , Takashi Hisada , Akihiro Horibe , Sayuri Hada , Eiji I. Nakamura , Kuniaki Sueoka
IPC分类号： H01L21/768 , H01L23/498 , H01L23/48
摘要： A via structure for electric connection is disclosed. The via structure includes a substrate that has a first surface and a via hole opened to the first surface. The via structure includes also a stress buffer layer disposed on the first surface of the substrate, which has an opening aligned to the via hole of the substrate. The via structure further includes a conductive body formed in the via hole of the substrate at least up to the level of the first surface of the substrate. In the via structure, the stress buffer layer receives the conductive body extending into the opening over the level of the first surface of the substrate and/or covers, at least in part, the edge of the first surface around the via hole of the substrate.

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