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1. 发明授权

US10110409B1 Multi-nyquist zone analog-to-digital converter (ADC) 有权
公开(公告)号：US10110409B1
公开(公告)日：2018-10-23
申请号：US15964186
申请日：2018-04-27
申请人： IQ-Analog Corporation
发明人： Michael Kappes , Steven R. Norsworthy
IPC分类号： H03M1/00 , H04L27/26 , H04L5/00 , H04L27/20 , H03M3/00 , H04L27/00 , H04B1/04
摘要： A multi-zone analog-to-digital converter (ADC) is provided that includes a track-and-hold (T/H) stage having a bandwidth of L Hertz (Hz) to accept an analog input signal, a clock input to accept a clock signal with a clock frequency of P Hz, and N deinterleaved signal outputs with a combined bandwidth of M Hz. N×(P/2)=M, L>Q×M, and Q is an integer >1. The T/H stage is able to sample an analog input signal in the Qth Nyquist Zone, where Q is an integer. A quantizer stage has N interleaved signal inputs connected to corresponding T/H stage signal outputs, a clock input to accept the clock signal, and an output to supply a digital output signal having a bandwidth of M Hz. A packaging interface typically connects the T/H stage to the quantizer stage, and has a bandwidth less than the clock frequency.

2. 发明授权

US08917124B1 Frequency multiplier jitter correction 有权
标题翻译：倍频器抖动校正
公开(公告)号：US08917124B1
公开(公告)日：2014-12-23
申请号：US14503656
申请日：2014-10-01
申请人： IQ-Analog Corporation
发明人： Mikko Waltari , Michael Kappes , William Huff
IPC分类号： H03L7/06 , H03L7/091 , H03L7/093 , H03L7/097
CPC分类号： H03L7/091 , H03L7/093 , H03L7/097 , H03L7/18 , H03L7/1806 , H03L2207/10 , H03L2207/50 , H03M1/0626 , H03M1/0836 , H03M1/12 , H03M1/1215 , H03M1/1245
摘要： A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.
摘要翻译：提供了一种用于倍频抖动校正的系统和方法。该方法接受具有第一频率的模拟参考信号，并且使用模拟参考信号导出具有大于第一频率的第二频率的系统时钟信号。使用压控振荡器（VCO）的PLL是倍频器的一个例子。该方法使用系统时钟信号对模拟参考信号的振幅进行采样，并将采样的模拟参考信号转换为数字化参考信号。响应于将数字化参考信号与理想数字化参考信号进行比较，导出系统时钟信号的相位误差校正。在第一时刻的相位误差校正可以应用于数字化数据信号，该数字化数据信号是先前从系统时钟信号在第一时刻采样的模拟数据信号转换的。

3. 发明申请

US20150061905A1 System and Method for Customizing Data Converters from Universal Function Dice 有权
标题翻译：通用功能骰子定制数据转换器的系统和方法
公开(公告)号：US20150061905A1
公开(公告)日：2015-03-05
申请号：US14537587
申请日：2014-11-10
申请人： IQ-Analog Corporation
发明人： Michael Kappes
IPC分类号： H03M1/10 , H03M1/66 , H03M1/12
CPC分类号： H03M1/1071 , H03M1/005 , H03M1/12 , H03M1/66
摘要： A method is provided for supplying a customized data converter fabricated from a universal function die. The method initially fabricates a plurality of universal data converter dice. Each universal data converter die is capable of performing a first plurality of data conversion algorithms. After the dice are made, each universal data converter die is tested to verify the performance of the first plurality of data conversion algorithms. Subsequently, a request is received for a customized data converter capable of performing a first data conversion function, which is selected from among the first plurality of data conversion algorithms. The method then fabricates a customized data converter capable of performing the first data conversion function, using a tested universal data converter die. The unselected data converter functions are disabled (not enabled). A configuration interface may be used to enable the requested data conversion function.
摘要翻译：提供了一种用于提供由通用功能模具制造的定制数据转换器的方法。该方法最初制造了多个通用数据转换器骰子。每个通用数据转换器管芯能够执行第一多个数据转换算法。在制作骰子之后，测试每个通用数据转换器管芯以验证第一多个数据转换算法的性能。随后，对于能够执行从第一多个数据转换算法中选择的第一数据转换功能的定制数据转换器，接收到请求。然后，该方法使用测试的通用数据转换器芯片制造能够执行第一数据转换功能的定制数据转换器。未选择的数据转换器功能被禁用（未启用）。可以使用配置接口来启用所请求的数据转换功能。

4. 发明申请

US20190013821A1 Multi-Nyquist Zone Digital-to-Analog Converter (DAC) 审中-公开
公开(公告)号：US20190013821A1
公开(公告)日：2019-01-10
申请号：US16012858
申请日：2018-06-20
申请人： IQ-Analog Corporation
发明人： Michael Kappes , Steven R. Norsworthy , Costantino Pala
IPC分类号： H03M1/66 , H04B1/44
摘要： A multi-zone digital-to-analog device is provided with a digital-to-analog (D/A) stage having an input to accept a digital input signal with a data bandwidth of M Hertz (Hz), a clock input to accept a clock signal with a clock frequency of P Hz, and an output to supply an analog value having a bandwidth of M Hz. An upsampling stage has an input to accept the analog value and a clock input to accept the clock signal. The upsampling stage has a device bandwidth of L Hz to supply an analog output signal with a full power bandwidth of K Hz, where (P/2)=M and M

5. 发明授权

US08957796B2 System clock jitter correction 有权
标题翻译：系统时钟抖动校正
公开(公告)号：US08957796B2
公开(公告)日：2015-02-17
申请号：US14507563
申请日：2014-10-06
申请人： IQ-Analog Corporation
发明人： Mikko Waltari , Michael Kappes , William Huff
IPC分类号： H03M1/06 , H03M1/12 , H03L7/091
CPC分类号： H03L7/091 , H03L7/093 , H03L7/097 , H03L7/18 , H03L7/1806 , H03L2207/10 , H03L2207/50 , H03M1/0626 , H03M1/0836 , H03M1/12 , H03M1/1215 , H03M1/1245
摘要： A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.
摘要翻译：提供了一种用于倍频抖动校正的系统和方法。该方法接受具有第一频率的模拟参考信号，并且使用模拟参考信号导出具有大于第一频率的第二频率的系统时钟信号。使用压控振荡器（VCO）的PLL是倍频器的一个例子。该方法使用系统时钟信号对模拟参考信号的振幅进行采样，并将采样的模拟参考信号转换为数字化参考信号。响应于将数字化参考信号与理想数字化参考信号进行比较，导出系统时钟信号的相位误差校正。在第一时刻的相位误差校正可以应用于数字化数据信号，该数字化数据信号是先前从系统时钟信号在第一时间采样的模拟数据信号转换的。

6. 发明申请

US20150015313A1 FREQUENCY MULTIPLIER JITTER CORRECTION 有权
标题翻译：频率多路径抖动校正
公开(公告)号：US20150015313A1
公开(公告)日：2015-01-15
申请号：US14503656
申请日：2014-10-01
申请人： IQ-Analog Corporation
发明人： Mikko Waltari , Michael Kappes , William Huff
IPC分类号： H03L7/091 , H03L7/097 , H03L7/093
CPC分类号： H03L7/091 , H03L7/093 , H03L7/097 , H03L7/18 , H03L7/1806 , H03L2207/10 , H03L2207/50 , H03M1/0626 , H03M1/0836 , H03M1/12 , H03M1/1215 , H03M1/1245
摘要： A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.
摘要翻译：提供了一种用于倍频抖动校正的系统和方法。该方法接受具有第一频率的模拟参考信号，并且使用模拟参考信号导出具有大于第一频率的第二频率的系统时钟信号。使用压控振荡器（VCO）的PLL是倍频器的一个例子。该方法使用系统时钟信号对模拟参考信号的振幅进行采样，并将采样的模拟参考信号转换为数字化参考信号。响应于将数字化参考信号与理想数字化参考信号进行比较，导出系统时钟信号的相位误差校正。在第一时刻的相位误差校正可以应用于数字化数据信号，该数字化数据信号是先前从系统时钟信号在第一时间采样的模拟数据信号转换的。

7. 发明授权

US10033398B1 Multi-zone digital-to-analog converter (DAC) 有权
公开(公告)号：US10033398B1
公开(公告)日：2018-07-24
申请号：US15787298
申请日：2017-10-18
申请人： IQ-Analog Corporation
发明人： Michael Kappes , Steven R. Norsworthy , Costantino Pala
IPC分类号： H03M1/00 , H03M1/66 , H04B1/44 , H03L7/08 , G11C27/02
摘要： A multi-zone digital-to-analog device is provided with a digital-to-analog (D/A) stage having an input to accept a digital input signal with a data bandwidth of M Hertz (Hz), a clock input to accept a clock signal with a clock frequency of P Hz, and an output to supply an analog value having a bandwidth of M Hz. An upsampling stage has an input to accept the analog value and a clock input to accept the clock signal. The upsampling stage has a device bandwidth of L Hz to supply an analog output signal with a full power bandwidth of K Hz, where (P/2)=M and M

8. 发明授权

US09979582B1 Multi-zone analog-to-digital converter (ADC) 有权
公开(公告)号：US09979582B1
公开(公告)日：2018-05-22
申请号：US15673228
申请日：2017-08-09
申请人： IQ-Analog Corporation
发明人： Michael Kappes , Steven R. Norsworthy
IPC分类号： H03M1/00 , H04L27/26 , H03M3/00 , H04L27/20 , H04L5/00 , H04B1/04 , H04L27/00
CPC分类号： H04L27/2666 , H03M1/06 , H03M1/121 , H03M3/496 , H04B2001/0491 , H04L5/0008 , H04L27/2092 , H04L2027/0081
摘要： A multi-zone analog-to-digital converter (ADC) is provided that includes a track-and-hold (T/H) stage having a bandwidth of L Hertz (Hz) to accept an analog input signal, a clock input to accept a clock signal with a clock frequency of P Hz, and N deinterleaved signal outputs with a combined bandwidth of M Hz. N×(P/2)=M, L>Q×M, and Q is an integer >1. The T/H stage is able to sample an analog input signal in the Qth Nyquist Zone, where Q is an integer. A quantizer stage has N interleaved signal inputs connected to corresponding T/H stage signal outputs, a clock input to accept the clock signal, and an output to supply a digital output signal having a bandwidth of M Hz. A packaging interface typically connects the T/H stage to the quantizer stage, and has a bandwidth less than the clock frequency.

9. 发明授权

US09258004B2 Customized data converters 有权
标题翻译：定制数据转换器
公开(公告)号：US09258004B2
公开(公告)日：2016-02-09
申请号：US14656880
申请日：2015-03-13
申请人： IQ-Analog Corporation
发明人： Michael Kappes
IPC分类号： H03M1/10 , H03M1/00 , H03M1/12 , H03M1/66
CPC分类号： H03M1/1071 , H03M1/005 , H03M1/12 , H03M1/66
摘要： A method is provided for supplying a customized data converter fabricated from a universal function die. The method initially fabricates a plurality of universal data converter dice. Each universal data converter die is capable of performing a first plurality of data conversion algorithms. After the dice are made, each universal data converter die is tested to verify the performance of the first plurality of data conversion algorithms. Subsequently, a request is received for a customized data converter capable of performing a first data conversion function, which is selected from among the first plurality of data conversion algorithms. The method then fabricates a customized data converter capable of performing the first data conversion function, using a tested universal data converter die. The unselected data converter functions are disabled (not enabled). A configuration interface may be used to enable the requested data conversion function.
摘要翻译：提供了一种用于提供由通用功能模具制造的定制数据转换器的方法。该方法最初制造了多个通用数据转换器骰子。每个通用数据转换器管芯能够执行第一多个数据转换算法。在制作骰子之后，测试每个通用数据转换器管芯以验证第一多个数据转换算法的性能。随后，对于能够执行从第一多个数据转换算法中选择的第一数据转换功能的定制数据转换器，接收到请求。然后，该方法使用测试的通用数据转换器芯片制造能够执行第一数据转换功能的定制数据转换器。未选择的数据转换器功能被禁用（未启用）。可以使用配置接口来启用所请求的数据转换功能。

10. 发明授权

US09019137B1 Multiplying digital-to-analog converter 有权
标题翻译：乘数字模拟转换器
公开(公告)号：US09019137B1
公开(公告)日：2015-04-28
申请号：US14158299
申请日：2014-01-17
申请人： IQ-Analog Corporation
发明人： Mikko Waltari , Michael Kappes
IPC分类号： H03M1/66 , H03M1/08 , H03M1/70 , H03M1/80
CPC分类号： H03M1/1245 , H03M1/804
摘要： A charge canceling multiplying digital-to-analog converter (MDAC) is provided with a reference block having inputs to accept reference voltages each sample clock cycle. The MDAC includes a sampling block having inputs to accept differential analog input voltage signals each sample clock cycle. A differential amplifier has a negative input and positive input connected to the reference block and sampling block to receive differential amplifier input signals, and a positive output and a negative output to supply differential output voltage signals each amplify clock cycle. The sampling section includes a first pair of feedback capacitors connected between the differential amplifier negative input and positive output, and a second pair of feedback capacitors connected between the differential amplifier positive input and negative output each amplify clock cycle. A capacitor from the first pair of parallel feedback capacitors is swapped with a capacitor from the second pair prior to each sample clock cycle.
摘要翻译：电荷消除乘法数模转换器（MDAC）具有参考块，其具有输入以接受每个采样时钟周期的参考电压。 MDAC包括具有输入的采样块，每个采样时钟周期接受差分模拟输入电压信号。差分放大器具有负输入和正输入，连接到参考块和采样块以接收差分放大器输入信号，以及正输出和负输出，以提供差分输出电压信号，每个放大时钟周期。采样部分包括连接在差分放大器负输入和正输出之间的第一对反馈电容器，连接在差分放大器正输入和负输出之间的第二对反馈电容器每个放大时钟周期。在每个采样时钟周期之前，来自第一对并联反馈电容器的电容器与来自第二对的电容器交换。

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