专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09105470B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09105470B2
公开(公告)日：2015-08-11
申请号：US14249505
申请日：2014-04-10
申请人： Infineon Technologies Austria AG
发明人： Gerhard Noebauer , Christoph Kadow , Donald Dibra , Robert Illing
IPC分类号： H01L29/78 , H01L27/02
CPC分类号： H01L27/0251
摘要： A switching component includes a control element and an integrated circuit. The integrated circuit includes a first transistor element and a second transistor element electrically connected in parallel to the first transistor element. The first transistor element includes first transistors, gate electrodes of which are disposed in first trenches in a first main surface of a semiconductor substrate. The second transistor element includes second transistors, gate electrodes of which are disposed in second trenches in the first main surface, and a second gate conductive line in contact with the gate electrodes in the second trenches. The control element is configured to control a potential applied to the second gate conductive line.
摘要翻译：开关部件包括控制元件和集成电路。集成电路包括与第一晶体管元件并联电连接的第一晶体管元件和第二晶体管元件。第一晶体管元件包括第一晶体管，其栅电极设置在半导体衬底的第一主表面中的第一沟槽中。第二晶体管元件包括第二晶体管，栅电极设置在第一主表面中的第二沟槽中，第二栅极导线与第二沟槽中的栅电极接触。控制元件被配置为控制施加到第二栅极导电线的电位。

2. 发明申请

US20170154965A1 Semiconductor Device 审中-公开
公开(公告)号：US20170154965A1
公开(公告)日：2017-06-01
申请号：US15361249
申请日：2016-11-25
申请人： Infineon Technologies Austria AG
发明人： Ralf Siemieniec , Oliver Blank , Marion Hoja , Christoph Kadow , Sabine Konrad , Cedric Ouvrard
IPC分类号： H01L29/417 , H01L29/739 , H01L29/06 , H01L29/78
CPC分类号： H01L29/41741 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/417 , H01L29/41708 , H01L29/41766 , H01L29/7396 , H01L29/7397 , H01L29/7813
摘要： A semiconductor device includes a semiconductor substrate including, between a bottom side and a top side, a first trench and a second trench extending in a vertical direction, and a contact groove arranged between the first trench and the second trench. The contact groove has a longitudinal extension in a plane perpendicular to the vertical direction. The longitudinal extension of the contact groove at least partially has a wave-shape.

3. 发明申请

US20150311195A1 Integrated Transistor Structure Having a Power Transistor and a Bipolar Transistor 有权
标题翻译：具有功率晶体管和双极晶体管的集成晶体管结构
公开(公告)号：US20150311195A1
公开(公告)日：2015-10-29
申请号：US14791577
申请日：2015-07-06
申请人： Infineon Technologies Austria AG
发明人： Christoph Kadow , Thorsten Meyer , Norbert Krischke
IPC分类号： H01L27/06 , H01L29/73 , H01L29/06 , H01L29/40 , H01L29/78 , H01L29/417 , H01L29/732
CPC分类号： H01L29/7813 , H01L27/0623 , H01L29/0696 , H01L29/402 , H01L29/407 , H01L29/41708 , H01L29/42368 , H01L29/4238 , H01L29/66666 , H01L29/7302 , H01L29/732 , H01L29/7825 , H01L29/7828
摘要： An integrated transistor structure includes an epitaxial layer on a semiconductor substrate, a power transistor formed in a first region of the epitaxial layer and having a drain region, a source region and a body region shorted to the source region, a bipolar transistor formed in a second region of the epitaxial layer spaced apart from the power transistor. A first trench structure formed in the epitaxial layer adjacent at least two opposing lateral sides of the power transistor includes a gate electrode spaced apart from a channel region of the power transistor by an insulating material. A second trench structure formed in the epitaxial layer adjacent at least two opposing lateral sides of the bipolar transistor includes a trench electrode spaced apart from the epitaxial layer by an insulating material. The gate electrode, base and emitter of the bipolar transistor are connected to different contacts isolated from one another.
摘要翻译：集成晶体管结构包括在半导体衬底上的外延层，形成在外延层的第一区域中的功率晶体管，并且具有漏极区域，源极区域和与源极区域短接的体区域，双极晶体管形成在所述外延层的第二区域与所述功率晶体管间隔开。形成在与功率晶体管的至少两个相对侧面相邻的外延层中的第一沟槽结构包括通过绝缘材料与功率晶体管的沟道区间隔开的栅电极。形成在外延层中的与双极晶体管的至少两个相对的横向侧相邻的第二沟槽结构包括通过绝缘材料与外延层隔开的沟槽电极。双极晶体管的栅极，基极和发射极连接到彼此隔离的不同触点。

4. 发明授权

US09646855B2 Semiconductor device with metal carrier and manufacturing method 有权
公开(公告)号：US09646855B2
公开(公告)日：2017-05-09
申请号：US14711198
申请日：2015-05-13
申请人： Infineon Technologies Austria AG
发明人： Oliver Haeberlen , Walter Rieger , Christoph Kadow , Markus Zundel
IPC分类号： H01L21/683 , H01L31/0304 , H01L21/48 , H01L29/06 , H01L29/417 , H01L29/66 , H01L29/778 , H01L21/768 , H01L29/20
CPC分类号： H01L21/4871 , H01L21/76879 , H01L29/0626 , H01L29/2003 , H01L29/41766 , H01L29/66462 , H01L29/7787 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor device including a metal carrier substrate. Above the carrier substrate a first semiconductor layer of Alx1Gay1Inz1N (x1+y1+z1=1, x1≧0, y1≧0, z1≧0) is formed. A second semiconductor layer of Alx2Gay2Inz2N (x2+y2+z2=1, x2>x1, y2≧0, z2≧0) is arranged on the first semiconductor layer and a gate region is arranged on the second semiconductor layer. The semiconductor device furthermore includes a source region and a drain region, wherein one of these regions is electrically coupled to the metal carrier substrate and includes a conductive region extending through the first semiconductor layer.

5. 发明申请

US20150249020A1 SEMICONDUCTOR DEVICE WITH METAL CARRIER AND MANUFACTURING METHOD 有权
标题翻译：具有金属载体和制造方法的半导体器件
公开(公告)号：US20150249020A1
公开(公告)日：2015-09-03
申请号：US14711198
申请日：2015-05-13
申请人： Infineon Technologies Austria AG
发明人： Oliver Haeberlen , Walter Rieger , Christoph Kadow , Markus Zundel
IPC分类号： H01L21/48 , H01L21/768
CPC分类号： H01L21/4871 , H01L21/76879 , H01L29/0626 , H01L29/2003 , H01L29/41766 , H01L29/66462 , H01L29/7787 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor device including a metal carrier substrate. Above the carrier substrate a first semiconductor layer of Alx1Gay1Inz1N (x1+y1+z1=1, x1≧0, y1≧0, z1≧0) is formed. A second semiconductor layer of Alx2Gay2Inz2N (x2+y2+z2=1, x2>x1, y2≧0, z2≧0) is arranged on the first semiconductor layer and a gate region is arranged on the second semiconductor layer. The semiconductor device furthermore includes a source region and a drain region, wherein one of these regions is electrically coupled to the metal carrier substrate and includes a conductive region extending through the first semiconductor layer.
摘要翻译：包括金属载体衬底的半导体器件。在载体基板上形成Al x1Gay1Inz1N（x1 + y1 + z1 = 1，x1≥0，y1≥0，z1≥0）的第一半导体层。 Alx2Gay2Inz2N（x2 + y2 + z2 = 1，x2> x1，y2≥0，z2≥0）的第二半导体层布置在第一半导体层上，并且在第二半导体层上布置栅极区。该半导体器件还包括源极区和漏极区，其中这些区中的一个电耦合到金属载体衬底并且包括延伸穿过第一半导体层的导电区。

6. 发明申请

US20140332877A1 Semiconductor Device 有权
标题翻译：半导体器件
公开(公告)号：US20140332877A1
公开(公告)日：2014-11-13
申请号：US14249505
申请日：2014-04-10
申请人： Infineon Technologies Austria AG
发明人： Gerhard Noebauer , Christoph Kadow , Donald Dibra , Robert Illing
IPC分类号： H01L27/02
CPC分类号： H01L27/0251
摘要： A switching component includes a control element and an integrated circuit. The integrated circuit includes a first transistor element and a second transistor element electrically connected in parallel to the first transistor element. The first transistor element includes first transistors, gate electrodes of which are disposed in first trenches in a first main surface of a semiconductor substrate. The second transistor element includes second transistors, gate electrodes of which are disposed in second trenches in the first main surface, and a second gate conductive line in contact with the gate electrodes in the second trenches. The control element is configured to control a potential applied to the second gate conductive line.
摘要翻译：开关部件包括控制元件和集成电路。集成电路包括与第一晶体管元件并联电连接的第一晶体管元件和第二晶体管元件。第一晶体管元件包括第一晶体管，其栅电极设置在半导体衬底的第一主表面中的第一沟槽中。第二晶体管元件包括第二晶体管，栅电极设置在第一主表面中的第二沟槽中，第二栅极导线与第二沟槽中的栅电极接触。控制元件被配置为控制施加到第二栅极导电线的电位。

7. 发明申请

US20140332881A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20140332881A1
公开(公告)日：2014-11-13
申请号：US13888546
申请日：2013-05-07
申请人： Infineon Technologies Austria AG
发明人： Gerhard Noebauer , Christoph Kadow , Donald Dibra , Robert Illing
IPC分类号： H01L27/088 , H01L29/78 , H01L27/105
CPC分类号： H01L27/088 , H01L21/823487 , H01L27/0207 , H01L27/105 , H01L29/407 , H01L29/42368 , H01L29/7813
摘要： A semiconductor device includes a transistor array, including first transistors and second transistors. Gate electrodes of the first transistors are disposed in first trenches in a first main surface of a semiconductor substrate, and gate electrodes of the second transistors are disposed in second trenches in the first main surface. The first and second trenches are disposed in parallel to each other. The semiconductor device further includes a first gate conductive line in contact with the gate electrodes in the first trenches, a second gate conductive line in contact with the gate electrodes in the second trenches, and a control element configured to control the potential applied to the second gate conductive line.
摘要翻译：半导体器件包括晶体管阵列，其包括第一晶体管和第二晶体管。第一晶体管的栅电极设置在半导体衬底的第一主表面中的第一沟槽中，第二晶体管的栅电极设置在第一主表面中的第二沟槽中。第一和第二沟槽彼此平行设置。半导体器件还包括与第一沟槽中的栅电极接触的第一栅极导电线，与第二沟槽中的栅电极接触的第二栅极导电线，以及控制元件，被配置为控制施加到第二沟槽栅极导线。

8. 发明授权

US09564425B2 Integrated transistor structure having a power transistor and a bipolar transistor 有权
标题翻译：具有功率晶体管和双极晶体管的集成晶体管结构
公开(公告)号：US09564425B2
公开(公告)日：2017-02-07
申请号：US14791577
申请日：2015-07-06
申请人： Infineon Technologies Austria AG
发明人： Christoph Kadow , Thorsten Meyer , Norbert Krischke
IPC分类号： H01L29/78 , H01L27/06 , H01L29/06 , H01L29/423 , H01L29/417 , H01L29/73 , H01L29/732 , H01L29/40 , H01L29/66
CPC分类号： H01L29/7813 , H01L27/0623 , H01L29/0696 , H01L29/402 , H01L29/407 , H01L29/41708 , H01L29/42368 , H01L29/4238 , H01L29/66666 , H01L29/7302 , H01L29/732 , H01L29/7825 , H01L29/7828
摘要： An integrated transistor structure includes an epitaxial layer on a semiconductor substrate, a power transistor formed in a first region of the epitaxial layer and having a drain region, a source region and a body region shorted to the source region, a bipolar transistor formed in a second region of the epitaxial layer spaced apart from the power transistor. A first trench structure formed in the epitaxial layer adjacent at least two opposing lateral sides of the power transistor includes a gate electrode spaced apart from a channel region of the power transistor by an insulating material. A second trench structure formed in the epitaxial layer adjacent at least two opposing lateral sides of the bipolar transistor includes a trench electrode spaced apart from the epitaxial layer by an insulating material. The gate electrode, base and emitter of the bipolar transistor are connected to different contacts isolated from one another.
摘要翻译：集成晶体管结构包括在半导体衬底上的外延层，形成在外延层的第一区域中的功率晶体管，并且具有漏极区域，源极区域和与源极区域短接的体区域，双极晶体管形成在所述外延层的第二区域与所述功率晶体管间隔开。形成在与功率晶体管的至少两个相对侧面相邻的外延层中的第一沟槽结构包括通过绝缘材料与功率晶体管的沟道区间隔开的栅电极。形成在外延层中的与双极晶体管的至少两个相对的横向侧相邻的第二沟槽结构包括通过绝缘材料与外延层隔开的沟槽电极。双极晶体管的栅极，基极和发射极连接到彼此隔离的不同触点。

9. 发明授权

US08907418B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08907418B2
公开(公告)日：2014-12-09
申请号：US13888546
申请日：2013-05-07
申请人： Infineon Technologies Austria AG
发明人： Gerhard Noebauer , Christoph Kadow , Donald Dibra , Robert Illing
IPC分类号： H01L29/78 , H01L27/088 , H01L27/105
CPC分类号： H01L27/088 , H01L21/823487 , H01L27/0207 , H01L27/105 , H01L29/407 , H01L29/42368 , H01L29/7813
摘要： A semiconductor device includes a transistor array, including first transistors and second transistors. Gate electrodes of the first transistors are disposed in first trenches in a first main surface of a semiconductor substrate, and gate electrodes of the second transistors are disposed in second trenches in the first main surface. The first and second trenches are disposed in parallel to each other. The semiconductor device further includes a first gate conductive line in contact with the gate electrodes in the first trenches, a second gate conductive line in contact with the gate electrodes in the second trenches, and a control element configured to control the potential applied to the second gate conductive line.
摘要翻译：半导体器件包括晶体管阵列，其包括第一晶体管和第二晶体管。第一晶体管的栅电极设置在半导体衬底的第一主表面中的第一沟槽中，第二晶体管的栅电极设置在第一主表面中的第二沟槽中。第一和第二沟槽彼此平行设置。半导体器件还包括与第一沟槽中的栅电极接触的第一栅极导电线，与第二沟槽中的栅电极接触的第二栅极导电线，以及控制元件，被配置为控制施加到第二沟槽栅极导线。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式