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1. 发明授权

US08966345B2 Selective error correction in memory to reduce power consumption 有权
标题翻译：内存中的选择性错误校正可降低功耗
公开(公告)号：US08966345B2
公开(公告)日：2015-02-24
申请号：US13688028
申请日：2012-11-28
申请人： Intel Corporation
发明人： Christopher B. Wilkerson , Alaa R. Alameldeen , Shih-Lien L. Lu
IPC分类号： H03M13/00 , G06F11/08
CPC分类号： G06F11/08 , G06F11/1052
摘要： Embodiments of apparatus, methods, systems, and devices are described herein for selective error correction in memory with multiple operation modes. In various embodiments, an error correction block (e.g., of a memory controller) may be configured to perform error correction on data read from a first portion of a memory based on a corresponding error correction code read from a second portion of the memory, and to calculate and store the error correction code. A control block coupled to the error correction block may be configured to selectively enable/disable the error correction block to perform the error correction, and to calculate and store the error correction code, based at least in part on a current operation mode of the memory.
摘要翻译：本文描述了用于具有多种操作模式的存储器中的选择性误差校正的装置，方法，系统和装置的实施例。在各种实施例中，错误校正块（例如，存储器控制器）可以被配置为基于从存储器的第二部分读取的对应的纠错码对存储器的第一部分读取的数据执行纠错，以及计算和存储纠错码。耦合到纠错块的控制块可以被配置为至少部分地基于存储器的当前操作模式来选择性地启用/禁用纠错块来执行纠错，并且计算和存储纠错码。

2. 发明授权

US10108549B2 Method and apparatus for pre-fetching data in a system having a multi-level system memory 有权
公开(公告)号：US10108549B2
公开(公告)日：2018-10-23
申请号：US14863255
申请日：2015-09-23
申请人： Intel Corporation
发明人： Zhe Wang , Christopher B. Wilkerson , Zeshan A. Chishti , Seth H. Pugsley , Alaa R. Alameldeen , Shih-Lien L. Lu
IPC分类号： G06F12/08 , G06F12/12 , G06F12/0862 , G06F12/0811 , G06F12/084
摘要： A method is described that includes creating a first data pattern access record for a region of system memory in response to a cache miss at a host side cache for a first memory access request. The first memory access request specifies an address within the region of system memory. The method includes fetching a previously existing data access pattern record for the region from the system memory in response to the cache miss. The previously existing data access pattern record identifies blocks of data within the region that have been previously accessed. The method includes pre-fetching the blocks from the system memory and storing the blocks in the cache.

3. 发明授权

US10884927B2 Cache architecture using way ID to reduce near memory traffic in a two-level memory system 有权
公开(公告)号：US10884927B2
公开(公告)日：2021-01-05
申请号：US15927715
申请日：2018-03-21
申请人： Intel Corporation
发明人： Zhe Wang , Alaa R. Alameldeen
IPC分类号： G06F12/0811 , G06F12/0804
摘要： One embodiment provides an apparatus. The apparatus includes last level cache circuitry and cache management circuitry. The last level cache circuitry stores cache blocks that at least partially include a subset of cache blocks stored by near memory circuitry. The near memory circuitry is configured in an n-way set associative format that references the cache blocks stored by the near memory circuitry using set identifiers and way identifiers. The cache management circuitry stores way identifiers for the cache blocks of the near memory circuitry within the cache blocks in the last level cache circuitry. Storing way identifiers in the cache blocks of the last level cache enables the cache management circuitry or memory controller circuitry to write back a cache block without reading tags in one or more ways of the near memory circuitry.

4. 发明授权

US10802883B2 Method, system, and device for near-memory processing with cores of a plurality of sizes 有权
公开(公告)号：US10802883B2
公开(公告)日：2020-10-13
申请号：US16107215
申请日：2018-08-21
申请人： INTEL CORPORATION
发明人： Alaa R. Alameldeen , Berkin Akin
IPC分类号： G06F9/50 , G06F9/48 , G06F1/329 , G06F13/42 , G06F1/3287 , G06F1/3206
摘要： A device is configured to be in communication with one or more host cores via a first communication path. A first set of processing-in-memory (PIM) cores and a second set of PIM cores are configured to be in communication with a memory included in the device over a second communication path, wherein the first set of PIM cores have greater processing power than the second set of PIM cores, and wherein the second communication path has a greater bandwidth for data transfer than the first communication path. Code offloaded by the one or more host cores are executed in the first set of PIM cores and the second set of PIM cores.

5. 发明申请

US20190095332A1 NEAR MEMORY MISS PREDICTION TO REDUCE MEMORY ACCESS LATENCY 审中-公开
公开(公告)号：US20190095332A1
公开(公告)日：2019-03-28
申请号：US15718071
申请日：2017-09-28
申请人： Intel Corporation
发明人： Zhe Wang , Zeshan A. Chishti , Alaa R. Alameldeen , Rajat Agarwal
IPC分类号： G06F12/0862 , G06F12/128 , G06F12/0888 , G06F12/0817 , G06F12/1009
CPC分类号： G06F12/0877 , G06F12/0822 , G06F12/0862 , G06F12/0888 , G06F12/1009 , G06F12/128 , G06F2212/602 , G06F2212/621
摘要： Systems, apparatuses and methods may provide for technology to maintain a prediction table that tracks missed page addresses with respect to a first memory. If an access request does not correspond to any valid page addresses in the prediction table, the access request may be sent to the first memory. If the access request corresponds to a valid page address in the prediction table, the access request may be sent to the first memory and a second memory in parallel, wherein the first memory is associated with a shorter access time than the second memory.

6. 发明授权

US09921972B2 Method and apparatus for implementing a heterogeneous memory subsystem 有权
公开(公告)号：US09921972B2
公开(公告)日：2018-03-20
申请号：US15281383
申请日：2016-09-30
申请人： Intel Corporation
发明人： Christopher B. Wilkerson , Alaa R. Alameldeen , Zeshan A. Chishti , Jaewoong Sim
IPC分类号： G06F12/00 , G06F12/122 , G11C7/10 , G06F3/06 , G06F12/0893
CPC分类号： G06F12/122 , G06F3/06 , G06F3/061 , G06F3/0644 , G06F3/0647 , G06F3/0673 , G06F12/0893 , G06F2212/1016 , G11C7/1072
摘要： An apparatus and method for implementing a heterogeneous memory subsystem is described. For example, one embodiment of a processor comprises: memory mapping logic to subdivide a system memory space into a plurality of memory chunks and to map the memory chunks across a first memory and a second memory, the first memory having a first set of memory access characteristics and the second memory having a second set of memory access characteristics different from the first set of memory access characteristics; and dynamic remapping logic to swap memory chunks between the first and second memories based, at least in part, on a detected frequency with which the memory chunks are accessed.

7. 发明授权

US09921961B2 Multi-level memory management 有权
公开(公告)号：US09921961B2
公开(公告)日：2018-03-20
申请号：US15400122
申请日：2017-01-06
申请人： Intel Corporation
发明人： Christopher B. Wilkerson , Alaa R. Alameldeen , Zhe Wang , Zeshan A. Chishti
IPC分类号： G11C16/04 , G06F12/0804 , G06F12/12
CPC分类号： G06F12/0804 , G06F12/0292 , G06F12/0868 , G06F12/0897 , G06F12/1009 , G06F12/1027 , G06F12/12 , G06F2212/1021 , G06F2212/502 , G06F2212/608 , G06F2212/651 , G11C8/00 , G11C11/56 , G11C16/08
摘要： A multi-level memory management circuit can remap data between near and far memory. In one embodiment, a register array stores near memory addresses and far memory addresses mapped to the near memory addresses. The number of entries in the register array is less than the number of pages in near memory. Remapping logic determines that a far memory address of the requested data is absent from the register array and selects an available near memory address from the register array. Remapping logic also initiates writing of the requested data at the far memory address to the selected near memory address. Remapping logic further writes the far memory address to an entry of the register array corresponding to the selected near memory address.

8. 发明授权

US09703708B2 System and method for thread scheduling on reconfigurable processor cores 有权
公开(公告)号：US09703708B2
公开(公告)日：2017-07-11
申请号：US14040142
申请日：2013-09-27
申请人： Intel Corporation
发明人： Alaa R. Alameldeen , Christopher B. Wilkerson , Eugene Gorbatov , Zeshan A. Chishti
IPC分类号： G06F12/08 , G06F9/50 , G06F12/0811 , G06F12/0842
CPC分类号： G06F12/0811 , G06F9/5061 , G06F12/0842 , G06F2209/5012 , Y02D10/13 , Y02D10/22 , Y02D10/36
摘要： Systems and methods for efficiently utilizing reconfigurable processor cores. An example processing system includes, for example, a control register comprising a plurality of inhibit bits, each inhibit bit indicating whether a corresponding processor core is allowed to merge with other processor cores; and dynamic core reallocation logic to temporarily merge a first processor core and a second processor core to speed execution of a first thread executed on the first processor core responsive to determining that a second thread executed on the second processor core has completed execution prior to a quantum associated with the second thread being reached and to determining that the inhibit bits indicate that the first and second cores may be merged.

9. 发明授权

US09472248B2 Method and apparatus for implementing a heterogeneous memory subsystem 有权
标题翻译：用于实现异构存储器子系统的方法和装置
公开(公告)号：US09472248B2
公开(公告)日：2016-10-18
申请号：US14228856
申请日：2014-03-28
申请人： Intel Corporation
发明人： Christopher B. Wilkerson , Alaa R. Alameldeen , Zeshan A. Chishti , Jaewoong Sim
IPC分类号： G06F3/06 , G11C7/10
CPC分类号： G06F12/122 , G06F3/06 , G06F3/061 , G06F3/0644 , G06F3/0647 , G06F3/0673 , G06F12/0893 , G06F2212/1016 , G11C7/1072
摘要： An apparatus and method for implementing a heterogeneous memory subsystem is described. For example, one embodiment of a processor comprises: memory mapping logic to subdivide a system memory space into a plurality of memory chunks and to map the memory chunks across a first memory and a second memory, the first memory having a first set of memory access characteristics and the second memory having a second set of memory access characteristics different from the first set of memory access characteristics; and dynamic remapping logic to swap memory chunks between the first and second memories based, at least in part, on a detected frequency with which the memory chunks are accessed.
摘要翻译：描述了用于实现异构存储器子系统的装置和方法。例如，处理器的一个实施例包括：存储器映射逻辑，用于将系统存储器空间细分成多个存储器块，并且跨越第一存储器和第二存储器映射存储器块，第一存储器具有第一组存储器访问特性和第二存储器具有不同于第一组存储器访问特性的第二组存储器存取特性; 以及动态重映射逻辑，用于至少部分地基于访问存储器块的检测频率来交换第一和第二存储器之间的存储器块。

10. 发明授权

US09223710B2 Read-write partitioning of cache memory 有权
标题翻译：高速缓存的读写分区
公开(公告)号：US09223710B2
公开(公告)日：2015-12-29
申请号：US13844823
申请日：2013-03-16
申请人： Intel Corporation
发明人： Alaa R. Alameldeen , Christopher B. Wilkerson , Samira M. Khan
IPC分类号： G06F12/00 , G06F12/08 , G06F12/12
CPC分类号： G06F12/0864 , G06F12/0804 , G06F12/0862 , G06F12/127 , G06F2212/604
摘要： A system and method to enforce read-write partitioning in an N-way, set associative cache may limit a number of ways allocated for storing modified data in a set to a value W and limit a number of ways holding read data to a value R. The cache may be configured where N=R+W. Furthermore, a number of ways storing prefetched read data may be limited to RP, while a number of ways storing prefetched modified data may be limited to WP. The values for W, R, WP, and/or RP may be determined using a prediction method to estimate cache miss rates for different values for W, R, WP, and/or RP and selecting values corresponding to a desired cache miss rate, and so allowing for selective application of the read-write partitioning.
摘要翻译：在N路设置关联高速缓存中强制执行读写分区的系统和方法可能限制分配用于将集合中的修改数据存储为值W的方式的数量，并限制将读取数据保存为值R的多种方式可以配置高速缓存，其中N = R + W。此外，存储预取的读取数据的多种方式可以限于RP，而存储预取修改数据的多种方式可能被限制为WP。可以使用预测方法来确定W，R，WP和/或RP的值，以估计用于W，R，WP和/或RP的不同值的高速缓存未命中率，并且选择对应于期望的高速缓存未命中率的值，因此允许选择性地应用读写分区。

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