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1. 发明授权

US09830988B2 Apparatus to reduce retention failure in complementary resistive memory 有权
公开(公告)号：US09830988B2
公开(公告)日：2017-11-28
申请号：US15187646
申请日：2016-06-20
申请人： Intel Corporation
发明人： Charles Augustine , Wei Wu , Shigeki Tomishima , Shih-Lien L. Lu , James W. Tschanz
IPC分类号： G11C13/00 , G11C11/16 , G11C7/10
CPC分类号： G11C13/0069 , G11C7/1006 , G11C11/1673 , G11C11/1675 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0021 , G11C13/0033 , G11C13/004 , G11C2013/0042 , G11C2213/79 , G11C2213/82
摘要： Described is an apparatus which comprises: a complementary resistive memory bit-cell; and a sense amplifier coupled to the complementary resistive memory bit-cell, wherein the sense amplifier includes: a first output node; and a first transistor which is operable to cause a deterministic output on the first output node.

2. 发明申请

US20170091445A1 TECHNOLOGIES FOR SOFTWARE ATTACK DETECTION USING ENCODED ACCESS INTENT 审中-公开
公开(公告)号：US20170091445A1
公开(公告)日：2017-03-30
申请号：US14866856
申请日：2015-09-26
申请人： Intel Corporation
发明人： Bin Xing , Krystof C. Zmudzinski , Wei Wu , Shih-Lien L. Lu , Carlos V. Rozas , Francis X. McKeen , Siddhartha Chhabra , Mark W. Shanahan
IPC分类号： G06F21/53
CPC分类号： G06F21/53 , G06F21/79 , G06F2221/033
摘要： Technologies for software attack detection include a computing device with a processor and a memory external to the processor. The processor originates a memory transaction with an associated secure enclave status bit that indicates whether the memory transaction originated in a secure execution mode, such as from a secure enclave. The processor computes an error-correcting code (ECC) based as a function of memory transaction data and the secure enclave status bit, and performs the memory transaction based on the ECC and the memory transaction data using the memory of the computing device. The processor may store the ECC and the memory transaction data to memory. The processor may load a stored ECC and data from the memory and compare the computed ECC to the stored ECC to detect memory transactions with an invalid secure enclave status bit. Other embodiments are described and claimed.

3. 发明授权

US09600183B2 Apparatus, system and method for determining comparison information based on memory data 有权
公开(公告)号：US09600183B2
公开(公告)日：2017-03-21
申请号：US14493130
申请日：2014-09-22
申请人： Intel Corporation
发明人： Shigeki Tomishima , Shih-Lien L. Lu
IPC分类号： G06F3/06 , G11C7/10 , G11C15/00
CPC分类号： G06F3/061 , G06F3/0665 , G06F3/0689 , G11C7/1006 , G11C7/1072 , G11C15/00
摘要： Techniques and mechanisms for determining comparison information at a memory device. In an embodiment, the memory device receives from a memory controller signals that include or otherwise indicate an address corresponding to a memory location of the memory device. Where it is determined that the signals indicate a compare operation, the memory device retrieves data stored at the memory location, and performs a comparison of the data to a reference data value that is included in or otherwise indicated by the received signals. The memory device sends to the memory controller information representing a result of the comparison. In another embodiment, a memory controller provides signals to control a compare operation by such a memory device.

4. 发明授权

US09418723B2 Techniques to reduce memory cell refreshes for a memory device 有权
标题翻译：减少内存设备刷新内存的技术
公开(公告)号：US09418723B2
公开(公告)日：2016-08-16
申请号：US14581762
申请日：2014-12-23
申请人： Intel Corporation
发明人： Zeshan A. Chishti , Ishwar Singh Bhati , Shih-Lien L. Lu
IPC分类号： G11C7/00 , G11C11/406 , G11C11/4094 , G11C11/4096
CPC分类号： G11C11/40611 , G11C11/40615 , G11C11/4072 , G11C11/4094 , G11C11/4096 , G11C2211/4065 , G11C2211/4067
摘要： Examples may include techniques to reduce memory cell refreshes for a memory device. These techniques include a control unit receiving a command to cause an internal refresh counter for the memory device to increment without causing one or more rows of an array of memory cells to be refreshed during an auto-refresh interval. In some examples, a memory controller has access to a refresh counter register at the memory device that may allow the memory controller to determine when to send the command that causes the internal refresh counter to increment without refreshing the one or more rows during the auto-refresh interval.
摘要翻译：示例可以包括用于减少存储器设备的存储器单元刷新的技术。这些技术包括控制单元，其接收使存储器件的内部刷新计数器增加的命令，而不会导致在自动刷新间隔期间刷新存储器单元阵列的一行或多行。在一些示例中，存储器控制器可访问存储器设备处的刷新计数器寄存器，其可以允许存储器控制器确定何时发送引起内部刷新计数器的命令增加，而不刷新自动存储器中的一行或多行，刷新间隔。

5. 发明授权

US10217493B2 DRAM data path sharing via a split local data bus 有权
公开(公告)号：US10217493B2
公开(公告)日：2019-02-26
申请号：US15940811
申请日：2018-03-29
申请人： INTEL CORPORATION
发明人： Wei Wu , Shigeki Tomishima , Shih-Lien L. Lu
IPC分类号： G06F13/00 , G11C7/06 , G06F13/16 , G06F13/40 , G06F13/42 , G11C7/10 , G11C11/406 , G11C11/4091 , G11C11/4093
摘要： Provided is memory device and a memory bank, comprising a global data bus, and a local data bus split into two parts, wherein the local data bus is configurable to direct signals to the global data bus. Provided also is a method in which signals are received in a local data bus that is split into two parts, and the signals are directed from the local data bus to the global data bus. Provided also is a computational device comprised of a processor and the memory device.

6. 发明授权

US09965415B2 DRAM data path sharing via a split local data bus and a segmented global data bus 有权
公开(公告)号：US09965415B2
公开(公告)日：2018-05-08
申请号：US14975293
申请日：2015-12-18
申请人： INTEL CORPORATION
发明人： Wei Wu , Shigeki Tomishima , Shih-Lien L. Lu
IPC分类号： G06F13/28 , G06F13/16 , G06F13/40
CPC分类号： G06F13/28 , G06F13/1668 , G06F13/4027
摘要： Provided are a memory device and a memory bank comprising a split local data bus, and a segmented global data bus coupled to local data bus. Provided also is a method comprising, receiving a signal from a split local data bus, and transmitting the signal to a segmented global data bus coupled to local data bus. Provided also is a computational device that includes the memory device and the memory bank, and optionally one or more of a display, a network interface, and a battery.

7. 发明申请

US20160299847A1 Instruction and Logic for Run-time Evaluation of Multiple Prefetchers 审中-公开
公开(公告)号：US20160299847A1
公开(公告)日：2016-10-13
申请号：US15190231
申请日：2016-06-23
申请人： Intel Corporation
发明人： Zeshan A. Chishti , Christopher B. Wilkerson , Seth Pugsley , Peng-Fei Chuang , Robert L. Scott , Aamer Jaleel , Shih-Lien L. Lu , Kingsum Chow
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F9/3802 , G06F9/3808 , G06F9/383 , G06F2212/6026
摘要： A processor includes a cache, a prefetcher module to select information according to a prefetcher algorithm, and a prefetcher algorithm selection module. The prefetcher algorithm selection module includes logic to select a candidate prefetcher algorithm determine and store memory addresses of predicted memory accesses of the candidate prefetcher algorithm when performed by the prefetcher module, determine cache lines accessed during memory operations, and evaluate whether the determined cache lines match the stored memory addresses. The prefetcher algorithm selection module further includes logic to adjust an accuracy ratio of the candidate prefetcher algorithm, compare the accuracy ratio with a threshold accuracy ratio, and determine whether to apply the first candidate prefetcher algorithm to the prefetcher module.

8. 发明申请

US20160034338A1 SEQUENTIAL CIRCUIT WITH ERROR DETECTION 有权
标题翻译：具有错误检测的顺序电路
公开(公告)号：US20160034338A1
公开(公告)日：2016-02-04
申请号：US14878985
申请日：2015-10-08
申请人： INTEL CORPORATION
发明人： Keith A. Bowman , James W. Tschanz , Nam Sung Kim , Janice C. Lee , Christopher B. Wilkerson , Shih-Lien L. Lu , Tanay Karnik , Vivek K. De
IPC分类号： G06F11/07
CPC分类号： G01R31/3177 , G01R31/31723 , G01R31/31725 , G01R31/31727 , G06F1/10 , G06F11/0706 , G06F11/0757 , G06F11/0793 , H03K3/0375
摘要： Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.
摘要翻译：提供了具有错误检测的顺序电路。例如，它们可以用于替代传统的主从触发器，例如在关键路径电路中，以检测并启动在顺序输入处的后期转换的校正。在一些实施例中，这样的顺序可以包括具有时间借用锁存器的转换检测器。

9. 发明授权

US08966345B2 Selective error correction in memory to reduce power consumption 有权
标题翻译：内存中的选择性错误校正可降低功耗
公开(公告)号：US08966345B2
公开(公告)日：2015-02-24
申请号：US13688028
申请日：2012-11-28
申请人： Intel Corporation
发明人： Christopher B. Wilkerson , Alaa R. Alameldeen , Shih-Lien L. Lu
IPC分类号： H03M13/00 , G06F11/08
CPC分类号： G06F11/08 , G06F11/1052
摘要： Embodiments of apparatus, methods, systems, and devices are described herein for selective error correction in memory with multiple operation modes. In various embodiments, an error correction block (e.g., of a memory controller) may be configured to perform error correction on data read from a first portion of a memory based on a corresponding error correction code read from a second portion of the memory, and to calculate and store the error correction code. A control block coupled to the error correction block may be configured to selectively enable/disable the error correction block to perform the error correction, and to calculate and store the error correction code, based at least in part on a current operation mode of the memory.
摘要翻译：本文描述了用于具有多种操作模式的存储器中的选择性误差校正的装置，方法，系统和装置的实施例。在各种实施例中，错误校正块（例如，存储器控制器）可以被配置为基于从存储器的第二部分读取的对应的纠错码对存储器的第一部分读取的数据执行纠错，以及计算和存储纠错码。耦合到纠错块的控制块可以被配置为至少部分地基于存储器的当前操作模式来选择性地启用/禁用纠错块来执行纠错，并且计算和存储纠错码。

10. 发明授权

US10102134B2 Instruction and logic for run-time evaluation of multiple prefetchers 有权
公开(公告)号：US10102134B2
公开(公告)日：2018-10-16
申请号：US15190231
申请日：2016-06-23
申请人： Intel Corporation
发明人： Zeshan A. Chishti , Christopher B. Wilkerson , Seth Pugsley , Peng-Fei Chuang , Robert L. Scott , Aamer Jaleel , Shih-Lien L. Lu , Kingsum Chow
IPC分类号： G06F9/38 , G06F12/0862 , G06F3/06 , G06F13/40
摘要： A processor includes a cache, a prefetcher module to select information according to a prefetcher algorithm, and a prefetcher algorithm selection module. The prefetcher algorithm selection module includes logic to select a candidate prefetcher algorithm determine and store memory addresses of predicted memory accesses of the candidate prefetcher algorithm when performed by the prefetcher module, determine cache lines accessed during memory operations, and evaluate whether the determined cache lines match the stored memory addresses. The prefetcher algorithm selection module further includes logic to adjust an accuracy ratio of the candidate prefetcher algorithm, compare the accuracy ratio with a threshold accuracy ratio, and determine whether to apply the first candidate prefetcher algorithm to the prefetcher module.

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