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1. 发明授权

US09817054B2 Electrical margining of multi-parameter high-speed interconnect links with multi-sample probing 有权
公开(公告)号：US09817054B2
公开(公告)日：2017-11-14
申请号：US13729756
申请日：2012-12-28
申请人： Intel Corporation
发明人： Thanunathan Rangarajan , Shreesh Chhabbi , Arvind A. Kumar , Venkatraman Iyer
IPC分类号： G01R31/04 , G01R31/30
CPC分类号： G01R31/04 , G01R31/30
摘要： Methods and apparatus relating to electrical margining of multi-parameter high-speed interconnect links with multi-sample probing are described. In one embodiment, logic is provided to generate one or more parameter values, corresponding to an electrical operating margin of an interconnect. The one or more parameter values are generated based on a plurality of eye observation sets to be detected in response to operation of the interconnect in accordance with a plurality of parameter sets (e.g., by using quantitative optimization techniques). In turn, the interconnect is to be operated at the one or more parameter values if it is determined that the one or more parameter values cause the interconnect to operate at an optimum level relative to an operation of the interconnect in accordance with one or more less optimum parameter levels. Other embodiments are also disclosed and claimed.

2. 发明授权

US09626321B2 High performance interconnect 有权
公开(公告)号：US09626321B2
公开(公告)日：2017-04-18
申请号：US14060191
申请日：2013-10-22
申请人： Intel Corporation
发明人： Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul R. Shah , Sitaraman V. Iyer , William Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
IPC分类号： G06F13/40 , G06F12/0831 , G06F13/42 , G06F9/30 , G06F12/0806 , H04L12/933 , G06F9/46 , G06F12/0813 , G06F12/0815 , H04L12/741 , G06F9/44
CPC分类号： G06F13/22 , G06F1/3287 , G06F8/71 , G06F8/73 , G06F8/77 , G06F9/30145 , G06F9/44505 , G06F9/466 , G06F11/1004 , G06F12/0806 , G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F13/4022 , G06F13/4068 , G06F13/4221 , G06F13/4282 , G06F13/4286 , G06F13/4291 , G06F2212/1016 , G06F2212/2542 , G06F2212/622 , H04L9/0662 , H04L12/4641 , H04L45/74 , H04L49/15 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D10/40 , Y02D10/44 , Y02D30/30
摘要： A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state

3. 发明申请

US20190391939A1 HIGH PERFORMANCE INTERCONNECT 审中-公开
公开(公告)号：US20190391939A1
公开(公告)日：2019-12-26
申请号：US16285035
申请日：2019-02-25
申请人： Intel Corporation
发明人： Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul R. Shah , Sitaraman V. Iyer , William Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
IPC分类号： G06F13/22 , G06F12/0808 , H04L9/06 , G06F13/42 , G06F11/10 , G06F13/40 , G06F1/3287 , G06F9/445 , G06F9/46 , G06F12/0831 , G06F12/0806 , G06F9/30 , G06F8/77 , G06F8/71 , G06F12/0815 , G06F12/0813 , H04L12/933
摘要： A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state

4. 发明申请

US20210117350A1 HIGH PERFORMANCE INTERCONNECT 有权
公开(公告)号：US20210117350A1
公开(公告)日：2021-04-22
申请号：US17134242
申请日：2020-12-25
申请人： Intel Corporation
发明人： Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul R. Shah , Sitaraman V. Iyer , William Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
IPC分类号： G06F13/22 , H04L12/933 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F13/42 , G06F8/71 , G06F8/77 , G06F9/30 , G06F12/0806 , G06F9/46 , G06F13/40 , G06F9/445 , G06F1/3287 , G06F11/10 , H04L9/06 , G06F12/0808
摘要： A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

5. 发明申请

US20180095927A1 HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER 审中-公开
公开(公告)号：US20180095927A1
公开(公告)日：2018-04-05
申请号：US15821401
申请日：2017-11-22
申请人： Intel Corporation
发明人： Venkatraman Iyer , Darren S. Jue , Rahul C. Shah , Arvind A. Kumar
IPC分类号： G06F13/42 , H04L12/933 , G06F9/30 , G06F9/445 , G06F9/46 , G06F13/40 , H04L12/46 , H04L12/741
CPC分类号： G06F13/22 , G06F1/3287 , G06F8/71 , G06F8/73 , G06F8/77 , G06F9/30145 , G06F9/44505 , G06F9/466 , G06F11/1004 , G06F12/0806 , G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F13/4022 , G06F13/4068 , G06F13/4221 , G06F13/4273 , G06F13/4282 , G06F13/4286 , G06F13/4291 , G06F2212/1016 , G06F2212/2542 , G06F2212/622 , H04L9/0662 , H04L12/4641 , H04L45/74 , H04L49/15 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D10/40 , Y02D10/44 , Y02D30/30
摘要： A serial data link is to be adapted during initialization of the link. Adaptation of the link is to include receiving a pseudorandom binary sequence (PRBS) from a remote agent, analyzing the PRBS to identify characteristics of the data link, and generating metric data describing the characteristics.

6. 发明授权

US10248591B2 High performance interconnect 有权
公开(公告)号：US10248591B2
公开(公告)日：2019-04-02
申请号：US15393153
申请日：2016-12-28
申请人： Intel Corporation
发明人： Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert H. Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul R. Shah , Sitaraman V. Iyer , William Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
IPC分类号： G06F13/22 , G06F12/0831 , G06F13/42 , G06F8/71 , G06F8/77 , G06F9/30 , G06F12/0806 , H04L12/933 , G06F9/46 , G06F13/40 , G06F12/0813 , G06F12/0815 , G06F9/445 , G06F1/3287 , G06F11/10 , H04L9/06 , G06F12/0808 , H04L12/741 , G06F8/73 , H04L12/46
摘要： A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

7. 发明授权

US09448663B2 Parallel touch point detection using processor graphics 有权
标题翻译：使用处理器图形的并行触摸点检测
公开(公告)号：US09448663B2
公开(公告)日：2016-09-20
申请号：US14129427
申请日：2013-06-28
申请人： Intel Corporation
发明人： Chaitanya R. Gandra , Balaji Vembu , Arvind A. Kumar , Nilesh V. Shah
IPC分类号： G06F3/041 , G06F3/0488 , G06T1/20
CPC分类号： G06F3/0418 , G06F3/0416 , G06F3/0488 , G06F2203/04104 , G06T1/20
摘要： Technologies for touch point detection include a computing device configured to receive input frames from a touch screen, identify touch point centroids and cluster boundaries, and track touch points. The computing device may group cells of the input frame into blocks. Using a processor graphics, the computing device may dispatch one thread per block to identify local maxima of the input frame and merge centroids within a touch distance threshold. The computing device may dispatch one thread per centroid to detect cluster boundaries. The computing device may dispatch one thread per previously identified touch point to assign an identifier of a previously tracked touch point to a touch point within a tracking distance threshold, remove duplicate identifiers, and assign unassigned identifiers to closest touch points. The computing device may dispatch one thread per block to assign unique identifiers to each unassigned touch point. Other embodiments are described and claimed.
摘要翻译：用于触摸点检测的技术包括被配置为从触摸屏接收输入帧，识别触摸点中心和群集边界以及跟踪触摸点的计算设备。计算设备可以将输入帧的单元分组成块。使用处理器图形，计算设备可以每个块分派一个线程以识别输入帧的局部最大值，并在触摸距离阈值内合并质心。计算设备可以调度每个质心一个线程来检测群集边界。计算设备可以调度每个先前识别的触摸点的一个线程，以将跟踪的触摸点的标识符分配给跟踪距离阈值内的触摸点，去除重复的标识符，并将未分配的标识符分配给最接近的接触点。计算设备可以每个块分派一个线程，以向每个未分配的触摸点分配唯一的标识符。描述和要求保护其他实施例。

8. 发明申请

US20220114122A1 HIGH PERFORMANCE INTERCONNECT 有权
公开(公告)号：US20220114122A1
公开(公告)日：2022-04-14
申请号：US17556853
申请日：2021-12-20
申请人： Intel Corporation
发明人： Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul R. Shah , Sitaraman V. Iyer , William Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
IPC分类号： G06F13/22 , H04L49/15 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F13/42 , G06F8/71 , G06F8/77 , G06F9/30 , G06F12/0806 , G06F9/46 , G06F13/40 , G06F9/445 , G06F1/3287 , G06F11/10 , H04L9/06 , G06F12/0808
摘要： A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

9. 发明授权

US11269793B2 High performance interconnect 有权
公开(公告)号：US11269793B2
公开(公告)日：2022-03-08
申请号：US16937499
申请日：2020-07-23
申请人： Intel Corporation
发明人： Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul R. Shah , Sitaraman V. Iyer , William Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
IPC分类号： G06F13/22 , H04L49/15 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F13/42 , G06F8/71 , G06F8/77 , G06F9/30 , G06F12/0806 , G06F9/46 , G06F13/40 , G06F9/445 , G06F1/3287 , G06F11/10 , H04L9/06 , G06F12/0808 , H04L45/74 , G06F8/73 , H04L12/46
摘要： A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

10. 发明申请

US20170109315A1 HIGH PERFORMANCE INTERCONNECT 审中-公开
公开(公告)号：US20170109315A1
公开(公告)日：2017-04-20
申请号：US15393153
申请日：2016-12-28
申请人： Intel Corporation
发明人： Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert H. Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul R. Shah , Sitaraman V. Iyer , William Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
IPC分类号： G06F13/42 , H04L9/06 , G06F11/10 , G06F13/40
CPC分类号： G06F13/22 , G06F1/3287 , G06F8/71 , G06F8/73 , G06F8/77 , G06F9/30145 , G06F9/44505 , G06F9/466 , G06F11/1004 , G06F12/0806 , G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F13/4022 , G06F13/4068 , G06F13/4221 , G06F13/4273 , G06F13/4282 , G06F13/4286 , G06F13/4291 , G06F2212/1016 , G06F2212/2542 , G06F2212/622 , H04L9/0662 , H04L12/4641 , H04L45/74 , H04L49/15 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D10/40 , Y02D10/44 , Y02D30/30
摘要： A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

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