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1. 发明申请

US20210117350A1 HIGH PERFORMANCE INTERCONNECT 有权
公开(公告)号：US20210117350A1
公开(公告)日：2021-04-22
申请号：US17134242
申请日：2020-12-25
申请人： Intel Corporation
发明人： Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul R. Shah , Sitaraman V. Iyer , William Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
IPC分类号： G06F13/22 , H04L12/933 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F13/42 , G06F8/71 , G06F8/77 , G06F9/30 , G06F12/0806 , G06F9/46 , G06F13/40 , G06F9/445 , G06F1/3287 , G06F11/10 , H04L9/06 , G06F12/0808
摘要： A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

2. 发明授权

US11513957B2 Processor and method implementing a cacheline demote machine instruction 有权
公开(公告)号：US11513957B2
公开(公告)日：2022-11-29
申请号：US17027248
申请日：2020-09-21
申请人： Intel Corporation
发明人： Ren Wang , Andrew J. Herdrich , Yen-cheng Liu , Herbert H. Hum , Jong Soo Park , Christopher J. Hughes , Namakkal N. Venkatesan , Adrian C. Moga , Aamer Jaleel , Zeshan A. Chishti , Mesut A. Ergin , Jr-shian Tsai , Alexander W. Min , Tsung-yuan C. Tai , Christian Maciocco , Rajesh Sankaran
IPC分类号： G06F12/0842 , G06F12/0893 , G06F12/109 , G06F12/0813 , G06F12/0831 , G06F9/455
摘要： Methods and apparatus implementing Hardware/Software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads. The apparatus include multi-core processors with multi-level cache hierarchies including and L1 and L2 cache for each core and a shared last-level cache (LLC). One or more machine-level instructions are provided for proactively demoting cachelines from lower cache levels to higher cache levels, including demoting cachelines from L1/L2 caches to an LLC. Techniques are also provided for implementing hardware/software co-optimization in multi-socket NUMA architecture system, wherein cachelines may be selectively demoted and pushed to an LLC in a remote socket. In addition, techniques are disclosure for implementing early snooping in multi-socket systems to reduce latency when accessing cachelines on remote sockets.

3. 发明授权

US10725920B2 Processors having virtually clustered cores and cache slices 有权
公开(公告)号：US10725920B2
公开(公告)日：2020-07-28
申请号：US15947831
申请日：2018-04-08
申请人： Intel Corporation
发明人： Herbert H. Hum , Brinda Ganesh , James R. Vash , Ganesh Kumar , Leena K. Puthiyedath , Scott J. Erlanger , Eric J. Dehaemer , Adrian C. Moga , Michelle M. Sebot , Richard L. Carlson , David Bubien , Eric Delano
IPC分类号： G06F12/00 , G06F12/0831 , G06F12/0811 , G06F12/084
摘要： A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

4. 发明授权

US09626321B2 High performance interconnect 有权
公开(公告)号：US09626321B2
公开(公告)日：2017-04-18
申请号：US14060191
申请日：2013-10-22
申请人： Intel Corporation
发明人： Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul R. Shah , Sitaraman V. Iyer , William Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
IPC分类号： G06F13/40 , G06F12/0831 , G06F13/42 , G06F9/30 , G06F12/0806 , H04L12/933 , G06F9/46 , G06F12/0813 , G06F12/0815 , H04L12/741 , G06F9/44
CPC分类号： G06F13/22 , G06F1/3287 , G06F8/71 , G06F8/73 , G06F8/77 , G06F9/30145 , G06F9/44505 , G06F9/466 , G06F11/1004 , G06F12/0806 , G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F13/4022 , G06F13/4068 , G06F13/4221 , G06F13/4282 , G06F13/4286 , G06F13/4291 , G06F2212/1016 , G06F2212/2542 , G06F2212/622 , H04L9/0662 , H04L12/4641 , H04L45/74 , H04L49/15 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D10/40 , Y02D10/44 , Y02D30/30
摘要： A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state

5. 发明申请

US20190391939A1 HIGH PERFORMANCE INTERCONNECT 审中-公开
公开(公告)号：US20190391939A1
公开(公告)日：2019-12-26
申请号：US16285035
申请日：2019-02-25
申请人： Intel Corporation
发明人： Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul R. Shah , Sitaraman V. Iyer , William Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
IPC分类号： G06F13/22 , G06F12/0808 , H04L9/06 , G06F13/42 , G06F11/10 , G06F13/40 , G06F1/3287 , G06F9/445 , G06F9/46 , G06F12/0831 , G06F12/0806 , G06F9/30 , G06F8/77 , G06F8/71 , G06F12/0815 , G06F12/0813 , H04L12/933
摘要： A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state

6. 发明授权

US10073779B2 Processors having virtually clustered cores and cache slices 有权
公开(公告)号：US10073779B2
公开(公告)日：2018-09-11
申请号：US13729579
申请日：2012-12-28
申请人： Intel Corporation
发明人： Herbert H. Hum , Brinda Ganesh , James R. Vash , Ganesh Kumar , Leena K. Puthiyedath , Scott J. Erlanger , Eric J. Dehaemer , Adrian C. Moga , Michelle M. Sebot , Richard L. Carlson , David Bubien , Eric Delano
IPC分类号： G06F12/00 , G06F12/0831 , G06F12/0811 , G06F12/084
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/084
摘要： A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

7. 发明申请

US20160188474A1 HARDWARE/SOFTWARE CO-OPTIMIZATION TO IMPROVE PERFORMANCE AND ENERGY FOR INTER-VM COMMUNICATION FOR NFVS AND OTHER PRODUCER-CONSUMER WORKLOADS 审中-公开
标题翻译：硬件/软件优化提高NFVS和其他生产者消费者工作量的互联网通信的性能和能源
公开(公告)号：US20160188474A1
公开(公告)日：2016-06-30
申请号：US14583389
申请日：2014-12-26
申请人： Intel Corporation
发明人： Ren Wang , Andrew J. Herdrich , Yen-cheng Liu , Herbert H. Hum , Jong Soo Park , Christopher J. Hughes , Namakkal N. Venkatesan , Adrian C. Moga , Aamer Jaleel , Zeshan A. Chishti , Mesut A. Ergin , Jr-shian Tsai , Alexander W. Min , Tsung-yuan C. Tai , Christian Maciocco , Rajesh Sankaran
IPC分类号： G06F12/08
CPC分类号： G06F12/0842 , G06F9/45558 , G06F12/0813 , G06F12/0833 , G06F12/0893 , G06F12/109 , G06F2009/45595 , G06F2212/1021 , G06F2212/283 , G06F2212/62 , Y02D10/13
摘要： Methods and apparatus implementing Hardware/Software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads. The apparatus include multi-core processors with multi-level cache hierarchies including and L1 and L2 cache for each core and a shared last-level cache (LLC). One or more machine-level instructions are provided for proactively demoting cachelines from lower cache levels to higher cache levels, including demoting cachelines from L1/L2 caches to an LLC. Techniques are also provided for implementing hardware/software co-optimization in multi-socket NUMA architecture system, wherein cachelines may be selectively demoted and pushed to an LLC in a remote socket. In addition, techniques are disclosure for implementing early snooping in multi-socket systems to reduce latency when accessing cachelines on remote sockets.
摘要翻译：实现硬件/软件协同优化的方法和设备，以提高NFV和其他生产者 - 消费者工作负载之间的VM间通信的性能和能量。该装置包括具有多级缓存层级的多核处理器，包括每个核心的L1和L2高速缓存以及共享的最后一级缓存（LLC）。提供了一个或多个机器级指令，用于主动地将高速缓存行从低级缓存级别降级到更高的高速缓存级别，包括将高速缓存行从L1 / L2高速缓存降级到LLC。还提供了用于在多插槽NUMA架构系统中实现硬件/软件协同优化的技术，其中高速缓存线可以被选择性地降级并被推送到远程插座中的LLC。此外，技术是在多插槽系统中实现早期窥探的技术，以减少在远程插槽上访问高速缓存线时的延迟。

8. 发明授权

US10248591B2 High performance interconnect 有权
公开(公告)号：US10248591B2
公开(公告)日：2019-04-02
申请号：US15393153
申请日：2016-12-28
申请人： Intel Corporation
发明人： Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert H. Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul R. Shah , Sitaraman V. Iyer , William Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
IPC分类号： G06F13/22 , G06F12/0831 , G06F13/42 , G06F8/71 , G06F8/77 , G06F9/30 , G06F12/0806 , H04L12/933 , G06F9/46 , G06F13/40 , G06F12/0813 , G06F12/0815 , G06F9/445 , G06F1/3287 , G06F11/10 , H04L9/06 , G06F12/0808 , H04L12/741 , G06F8/73 , H04L12/46
摘要： A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

9. 发明申请

US20170109286A1 HIGH PERFORMANCE INTERCONNECT COHERENCE PROTOCOL 审中-公开
公开(公告)号：US20170109286A1
公开(公告)日：2017-04-20
申请号：US15393577
申请日：2016-12-29
申请人： Intel Corporation
发明人： Robert G. Blankenship , Bahaa Fahim , Robert H. Beers , Yen-Cheng Liu , Vedaraman Geetha , Herbert H. Hum , Jeff Willey
IPC分类号： G06F12/0831 , G06F12/0808
CPC分类号： G06F13/22 , G06F1/3287 , G06F8/71 , G06F8/73 , G06F8/77 , G06F9/30145 , G06F9/44505 , G06F9/466 , G06F11/1004 , G06F12/0806 , G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F13/4022 , G06F13/4068 , G06F13/4221 , G06F13/4273 , G06F13/4282 , G06F13/4286 , G06F13/4291 , G06F2212/1016 , G06F2212/2542 , G06F2212/622 , H04L9/0662 , H04L12/4641 , H04L45/74 , H04L49/15 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D10/40 , Y02D10/44 , Y02D30/30
摘要： A request is received that is to reference a first agent and to request a particular line of memory to be cached in an exclusive state. A snoop request is sent intended for one or more other agents. A snoop response is received that is to reference a second agent, the snoop response to include a writeback to memory of a modified cache line that is to correspond to the particular line of memory. A complete is sent to be addressed to the first agent, wherein the complete is to include data of the particular line of memory based on the writeback.

10. 发明授权

US09436605B2 Cache coherency apparatus and method minimizing memory writeback operations 有权
标题翻译：缓存一致性设备和最小化内存回写操作的方法
公开(公告)号：US09436605B2
公开(公告)日：2016-09-06
申请号：US14136131
申请日：2013-12-20
申请人： Intel Corporation
发明人： Jeffrey D. Chamberlain , Vedaraman Geetha , Robert G. Blankenship , Yen-Cheng Liu , Adrian C. Moga , Herbert H. Hum , Sailesh Kottapalli
IPC分类号： G06F12/08
CPC分类号： G06F12/0817 , G06F12/0815
摘要： An apparatus and method for reducing or eliminating writeback operations. For example, one embodiment of a method comprises: detecting a first operation associated with a cache line at a first requestor cache; detecting that the cache line exists in a first cache in a modified (M) state; forwarding the cache line from the first cache to the first requestor cache and storing the cache line in the first requestor cache in a second modified (M′) state; detecting a second operation associated with the cache line at a second requestor; responsively forwarding the cache line from the first requestor cache to the second requestor cache and storing the cache line in the second requestor cache in an owned (O) state if the cache line has not been modified in the first requestor cache; and setting the cache line to a shared (S) state in the first requestor cache.
摘要翻译：一种用于减少或消除写回操作的设备和方法。例如，方法的一个实施例包括：在第一请求者高速缓存处检测与高速缓存行相关联的第一操作; 检测到所述高速缓存行存在于修改（M）状态的第一高速缓存中; 将所述高速缓存行从所述第一高速缓存转发到所述第一请求者高速缓存，并且以第二修改（M'）状态将所述高速缓存行存储在所述第一请求程序高速缓存中; 在第二请求者处检测与所述高速缓存线相关联的第二操作; 响应地将所述高速缓存行从所述第一请求者缓存转发到所述第二请求器高速缓存，并且如果所述高速缓存行尚未在所述第一请求者高速缓存中被修改则将所述高速缓存行存储在所述第二请求程序高速缓存中; 以及将所述高速缓存行设置为所述第一请求者缓存中的共享（S）状态。

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