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1. 发明申请

US20210117343A1 ENFORCING MEMORY OPERAND TYPES USING PROTECTION KEYS 有权
公开(公告)号：US20210117343A1
公开(公告)日：2021-04-22
申请号：US17133734
申请日：2020-12-24
申请人： Intel Corporation
发明人： Michael Lemay , David A. Koufaty , Ravi L. Sahita
IPC分类号： G06F12/14 , G06F21/53 , G06F21/56
摘要： Enforcing memory operand types using protection keys is generally described herein. A processor system to provide sandbox execution support for protection key rights attacks includes a processor core to execute a task associated with an untrusted application and execute the task using a designated page of a memory; and a memory management unit to designate the page of the memory to support execution of the untrusted application.

2. 发明授权

US10664199B2 Application driven hardware cache management 有权
公开(公告)号：US10664199B2
公开(公告)日：2020-05-26
申请号：US16188950
申请日：2018-11-13
申请人： Intel Corporation
发明人： Subramanya R. Dulloor , Rajesh M. Sankaran , David A. Koufaty , Christopher J. Hughes , Jong Soo Park , Sheng Li
IPC分类号： G06F12/00 , G06F3/06 , G06F12/0888 , G06F9/50 , G06F12/08 , G06F12/02 , G06F12/1009 , G06F12/0866
摘要： A processor includes a processing core to generate a memory request for an application data in an application. The processor also includes a virtual page group memory management (VPGMM) unit coupled to the processing core to specify a caching priority (CP) to the application data for the application. The caching priority identifies importance of the application data in a cache.

3. 发明申请

US20180095892A1 PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO DETERMINE PAGE GROUP IDENTIFIERS, AND OPTIONALLY PAGE GROUP METADATA, ASSOCIATED WITH LOGICAL MEMORY ADDRESSES 审中-公开
公开(公告)号：US20180095892A1
公开(公告)日：2018-04-05
申请号：US15283355
申请日：2016-10-01
申请人： Intel Corporation
发明人： Hugh Wilkinson , William R. Wheeler , Shirish Aundhe , Sandhya Viswanathan , David A. Koufaty
IPC分类号： G06F12/1027 , G06F12/14 , G06F9/30
CPC分类号： G06F12/1027 , G06F9/3004 , G06F9/30076 , G06F9/30145 , G06F12/145 , G06F2212/1052 , G06F2212/68
摘要： A processor of an aspect includes a decode unit to decode an instruction. The instruction is to indicate source memory address information, and the instruction to indicate a destination architecturally-visible storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to store a result in the destination architecturally-visible storage location. The result is to include one of: (1) a page group identifier that is to correspond to a logical memory address that is to be based, at least in part, on the source memory address information; and (2) a set of page group metadata that is to correspond to the page group identifier. Other processors, methods, systems, and instructions are disclosed.

4. 发明授权

US09672046B2 Apparatus and method for intelligently powering heterogeneous processor components 有权
公开(公告)号：US09672046B2
公开(公告)日：2017-06-06
申请号：US13730493
申请日：2012-12-28
申请人： INTEL CORPORATION
发明人： Dheeraj R. Subbareddy , Ganapati N. Srinivasa , Eugene Gorbatov , Scott D. Hahn , David A. Koufaty , Paul Brett , Abirami Prabhakaran
IPC分类号： G06F1/26 , G06F9/44 , G06F1/32 , G06F9/50 , G09G5/36
CPC分类号： G06F9/44 , G06F1/324 , G06F1/329 , G06F1/3296 , G06F9/5094 , G09G5/363 , G09G2330/021 , Y02D10/126 , Y02D10/172 , Y02D10/22 , Y02D10/24
摘要： An intelligent power allocation architecture for a processor. For example, one embodiment of a processor comprises: a plurality of processor components for performing a corresponding plurality of processor functions; a plurality of power planes, each power plane associated with one of the processor components; and a power control unit (PCU) to dynamically adjust power to each of the power planes based on user experience metrics, workload characteristics, and power constraints for a current use of the processor.

5. 发明申请

US20160378651A1 APPLICATION DRIVEN HARDWARE CACHE MANAGEMENT 审中-公开
标题翻译：应用驱动硬件缓存管理
公开(公告)号：US20160378651A1
公开(公告)日：2016-12-29
申请号：US14748971
申请日：2015-06-24
申请人： Intel Corporation
发明人： Subramanya R. Dulloor , Rajesh M. Sankaran , David A. Koufaty , Christopher J. Hughes , Jong Soo Park , Sheng Li
IPC分类号： G06F12/08 , G06F3/06
CPC分类号： G06F3/0673 , G06F3/0604 , G06F3/0608 , G06F3/0638 , G06F3/0665 , G06F9/50 , G06F12/023 , G06F12/08 , G06F12/0866 , G06F12/0888 , G06F12/1009 , G06F2212/60 , G06F2212/684
摘要： A processor includes a processing core to generate a memory request for an application data in an application. The processor also includes a virtual page group memory management (VPGMM) unit coupled to the processing core to specify a caching priority (CP) to the application data for the application. The caching priority identifies importance of the application data in a cache.
摘要翻译：处理器包括处理核心，以在应用程序中生成应用程序数据的存储器请求。处理器还包括耦合到处理核心的虚拟页组存储器管理（VPGMM）单元，以指定应用程序的应用程序数据的缓存优先级（CP）。缓存优先级标识应用程序数据在缓存中的重要性。

6. 发明授权

US09910611B2 Access control for memory protection key architecture 有权
公开(公告)号：US09910611B2
公开(公告)日：2018-03-06
申请号：US14725130
申请日：2015-05-29
申请人： INTEL CORPORATION
发明人： David A. Koufaty , Ravi L. Sahita
IPC分类号： G06F12/00 , G06F3/06 , G06F12/14 , G06F12/1009 , G06F12/08
CPC分类号： G06F3/0622 , G06F3/0604 , G06F3/0637 , G06F3/0673 , G06F12/08 , G06F12/1009 , G06F12/14 , G06F12/145 , G06F12/1466 , G06F12/1475 , G06F2212/1052
摘要： A processing system includes a processing core to execute a task and a memory management unit, coupled to the core. The memory management unit includes a protection key register comprising a plurality of fields. Each field comprising a set of bits reflecting a memory access permission for each of a plurality of memory domains. The memory management unit also includes a plurality of protection key mask registers. Each of the protection key mask registers comprising a mask having a plurality of bits, each bit reflecting an access permission to a corresponding field of the protection key register by a code page residing in a memory domain of the plurality of memory domains identified by an index of the protection key mask register. The memory management unit is, responsive to receiving a request to modify the protection key register by the code page residing in the memory domain, to select a protection key mask register among the plurality of protection key mask registers and to apply a mask comprised by selected protection key mask register indexed by an identifier of the memory domain.

7. 发明授权

US09639372B2 Apparatus and method for heterogeneous processors mapping to virtual cores 有权
公开(公告)号：US09639372B2
公开(公告)日：2017-05-02
申请号：US13730565
申请日：2012-12-28
申请人： Intel Corporation
发明人： Paolo Narvaez , Ganapati N. Srinivasa , Eugene Gorbatov , Dheeraj R. Subbareddy , Mishali Naik , Alon Naveh , Abirami Prabhakaran , Eliezer Weissmann , David A. Koufaty , Paul Brett , Scott D. Hahn , Andrew J. Herdrich , Ravishankar Iyer , Nagabhushan Chitlur , Inder M. Sodhi , Gaurav Khanna , Russell J. Fenger
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3891
摘要： A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of large physical processor cores to software through a corresponding set of virtual cores and to hide the set of small physical processor core from the software.

8. 发明申请

US20160350019A1 ACCESS CONTROL FOR MEMORY PROTECTION KEY ARCHITECTURE 有权
标题翻译：存储器保护关键体系结构的访问控制
公开(公告)号：US20160350019A1
公开(公告)日：2016-12-01
申请号：US14725130
申请日：2015-05-29
申请人： INTEL CORPORATION
发明人： David A. Koufaty , Ravi L. Sahita
IPC分类号： G06F3/06
CPC分类号： G06F3/0622 , G06F3/0604 , G06F3/0637 , G06F3/0673 , G06F12/08 , G06F12/1009 , G06F12/14 , G06F12/145 , G06F12/1466 , G06F12/1475 , G06F2212/1052
摘要： A processing system includes a processing core to execute a task and a memory management unit, coupled to the core. The memory management unit includes a protection key register comprising a plurality of fields. Each field comprising a set of bits reflecting a memory access permission for each of a plurality of memory domains. The memory management unit also includes a plurality of protection key mask registers. Each of the protection key mask registers comprising a mask having a plurality of bits, each bit reflecting an access permission to a corresponding field of the protection key register by a code page residing in a memory domain of the plurality of memory domains identified by an index of the protection key mask register. The memory management unit is, responsive to receiving a request to modify the protection key register by the code page residing in the memory domain, to select a protection key mask register among the plurality of protection key mask registers and to apply a mask comprised by selected protection key mask register indexed by an identifier of the memory domain.
摘要翻译：处理系统包括执行任务的处理核心和耦合到核心的存储器管理单元。存储器管理单元包括包括多个场的保护密钥寄存器。每个字段包括反映多个存储器域中的每一个的存储器访问许可的一组位。存储器管理单元还包括多个保护密钥掩码寄存器。每个保护密钥掩码寄存器包括具有多个位的掩码，每个位反映由驻留在由索引识别的多个存储器域的存储器域中的代码页对保护密钥寄存器的相应字段的访问许可的保护键盘掩码寄存器。存储器管理单元响应于通过驻留在存储器域中的代码页接收到修改保护密钥寄存器的请求，以选择多个保护密钥掩码寄存器中的保护密钥掩码寄存器，并且应用由选择的掩码包括的掩码保护密钥掩码寄存器由存储器域的标识符索引。

9. 发明授权

US11537520B2 Remote atomic operations in multi-socket systems 有权
公开(公告)号：US11537520B2
公开(公告)日：2022-12-27
申请号：US17494651
申请日：2021-10-05
申请人： Intel Corporation
发明人： Doddaballapur N. Jayasimha , Samantika S. Sury , Christopher J. Hughes , Jonas Svennebring , Yen-Cheng Liu , Stephen R. Van Doren , David A. Koufaty
IPC分类号： G06F12/0815 , G06F12/0808 , G06F9/30 , G06F12/0817 , G06F12/0831
摘要： Disclosed embodiments relate to remote atomic operations (RAO) in multi-socket systems. In one example, a method, performed by a cache control circuit of a requester socket, includes: receiving the RAO instruction from the requester CPU core, determining a home agent in a home socket for the addressed cache line, providing a request for ownership (RFO) of the addressed cache line to the home agent, waiting for the home agent to either invalidate and retrieve a latest copy of the addressed cache line from a cache, or to fetch the addressed cache line from memory, receiving an acknowledgement and the addressed cache line, executing the RAO instruction on the received cache line atomically, subsequently receiving multiple local RAO instructions to the addressed cache line from one or more requester CPU cores, and executing the multiple local RAO instructions on the received cache line independently of the home agent.

10. 发明授权

US11436161B2 System for address mapping and translation protection 有权
公开(公告)号：US11436161B2
公开(公告)日：2022-09-06
申请号：US16686379
申请日：2019-11-18
申请人： Intel Corporation
发明人： Ravi L. Sahita , Gilbert Neiger , Vedvyas Shanbhogue , David M. Durham , Andrew V. Anderson , David A. Koufaty , Asit K. Mallick , Arumugam Thiyagarajah , Barry E. Huntley , Deepak K. Gupta , Michael Lemay , Joseph F. Cihula , Baiju V. Patel
IPC分类号： G06F12/00 , G06F12/14 , G06F9/455 , G06F12/1009 , G06F12/1027 , G06F21/78
摘要： This disclosure is directed to a system for address mapping and translation protection. In one embodiment, processing circuitry may include a virtual machine manager (VMM) to control specific guest linear address (GLA) translations. Control may be implemented in a performance sensitive and secure manner, and may be capable of improving performance for critical linear address page walks over legacy operation by removing some or all of the cost of page walking extended page tables (EPTs) for critical mappings. Alone or in combination with the above, certain portions of a page table structure may be selectively made immutable by a VMM or early boot process using a sub-page policy (SPP). For example, SPP may enable non-volatile kernel and/or user space code and data virtual-to-physical memory mappings to be made immutable (e.g., non-writable) while allowing for modifications to non-protected portions of the OS paging structures and particularly the user space.

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