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1. 发明授权

US10860244B2 Method and apparatus for multi-level memory early page demotion 有权
公开(公告)号：US10860244B2
公开(公告)日：2020-12-08
申请号：US15854357
申请日：2017-12-26
申请人： Intel Corporation
发明人： Binh Pham , Christopher B. Wilkerson , Alaa R. Alameldeen , Zeshan A. Chishti , Zhe Wang
IPC分类号： G06F3/06 , G06F12/0862 , G06F12/0871 , G06F12/1027 , G06F12/0897 , G06F12/1045 , G06F12/128 , G06F12/14 , G06F12/123
摘要： An apparatus is described that includes a memory controller to couple to a multi-level memory characterized by a faster higher level and a slower lower level. The memory controller having early demotion logic circuitry to demote a page from the higher level to the lower level without system software having to instruct the memory controller to demote the page and before the system software promotes another page from the lower level to the higher level.

2. 发明授权

US10678692B2 Method and system for coordinating baseline and secondary prefetchers 有权
公开(公告)号：US10678692B2
公开(公告)日：2020-06-09
申请号：US15709285
申请日：2017-09-19
申请人： INTEL CORPORATION
发明人： Seth H. Pugsley , Manjunath Shevgoor , Christopher B. Wilkerson
IPC分类号： G06F12/0862 , G06F9/30 , G06F12/0811 , G06F12/0806 , G06F12/0897
摘要： In one embodiment, a processor comprises a first prefetcher to generate prefetch requests to prefetch data into a mid-level cache; a second prefetcher to generate prefetch requests to prefetch data into the mid-level cache; and a prefetcher selector to select a prefetcher configuration for the first prefetcher and the second prefetcher based on at least one memory access metric, wherein the prefetcher configuration is to specify whether the first prefetcher is to be enabled to issue, to the mid-level cache, prefetch requests for data of a particular page and whether the second prefetcher is to be enabled to issue, to the mid-level cache, prefetch requests for data of the particular page.

3. 发明授权

US10606755B2 Method and system for performing data movement operations with read snapshot and in place write update 有权
公开(公告)号：US10606755B2
公开(公告)日：2020-03-31
申请号：US15640060
申请日：2017-06-30
申请人： Intel Corporation
发明人： Anil Vasudevan , Venkata Krishnan , Andrew J. Herdrich , Ren Wang , Robert G. Blankenship , Vedaraman Geetha , Shrikant M. Shah , Marshall A. Millier , Raanan Sade , Binh Q. Pham , Olivier Serres , Chyi-Chang Miao , Christopher B. Wilkerson
IPC分类号： G06F12/0868 , G06F12/0897 , G06F3/06 , G06F12/0811 , G06F12/0871
摘要： Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.

4. 发明授权

US10482017B2 Processor, method, and system for cache partitioning and control for accurate performance monitoring and optimization 有权
公开(公告)号：US10482017B2
公开(公告)日：2019-11-19
申请号：US15721223
申请日：2017-09-29
申请人： Intel Corporation
发明人： Karl I. Taht , Christopher B. Wilkerson , Ren Wang , James J. Greensky
IPC分类号： G06F12/08 , G06F12/0831 , G06F12/0846 , G06F12/128
摘要： Processor, method, and system for tracking partition-specific statistics across cache partitions that apply different cache management policies is described herein. One embodiment of a processor includes: a cache; a cache controller circuitry to partition the cache into a plurality of cache partitions based on one or more control addresses; a cache policy assignment circuitry to apply different cache policies to different subsets of the plurality of cache partitions; and a cache performance monitoring circuitry to track cache events separately for each of the cache partitions and to provide partition-specific statistics to allow comparison between the plurality of cache partitions as a result of applying the different cache policies in a same time period.

5. 发明授权

US10452551B2 Programmable memory prefetcher for prefetching multiple cache lines based on data in a prefetch engine control register 有权
公开(公告)号：US10452551B2
公开(公告)日：2019-10-22
申请号：US15376242
申请日：2016-12-12
申请人： Intel Corporation
发明人： Ganesh Venkatesh , Christopher B. Wilkerson , Seth H. Pugsley , Deborah T. Marr
IPC分类号： G06F12/08 , G06F9/30 , G06F12/0862
摘要： A processor may include a programmable memory prefetcher that includes a programmable hardware prefetch engine and a prefetch engine control register. The programmable memory prefetcher may include circuitry and may be configured to receive, during execution of an application, a first instruction for configuring the prefetch engine for prefetching multiple cache lines to be accessed in the future, at predictable locations, by the application; to store, in the prefetch engine control register, dependent on information in the first instruction, data representing an amount of prefetching to be performed, and data representing a stride distance between consecutive cache lines to be prefetched; to receive a second instruction for prefetching a single cache line whose location is identified in the second instruction; and to initiate, in response to receiving the second instruction, prefetching of multiple cache lines by the prefetch engine, to be performed in parallel with execution of the application and in accordance with the data stored in the prefetch engine control register. The prefetch engine control register may store multiple entries, each including an identifier of a given operation to prefetch multiple cache lines. An instruction may also be received to disable prefetching of multiple cache lines. The multiple cache lines may be prefetched from a last-level cache (LLC) to a mid-level cache.

6. 发明授权

US10102134B2 Instruction and logic for run-time evaluation of multiple prefetchers 有权
公开(公告)号：US10102134B2
公开(公告)日：2018-10-16
申请号：US15190231
申请日：2016-06-23
申请人： Intel Corporation
发明人： Zeshan A. Chishti , Christopher B. Wilkerson , Seth Pugsley , Peng-Fei Chuang , Robert L. Scott , Aamer Jaleel , Shih-Lien L. Lu , Kingsum Chow
IPC分类号： G06F9/38 , G06F12/0862 , G06F3/06 , G06F13/40
摘要： A processor includes a cache, a prefetcher module to select information according to a prefetcher algorithm, and a prefetcher algorithm selection module. The prefetcher algorithm selection module includes logic to select a candidate prefetcher algorithm determine and store memory addresses of predicted memory accesses of the candidate prefetcher algorithm when performed by the prefetcher module, determine cache lines accessed during memory operations, and evaluate whether the determined cache lines match the stored memory addresses. The prefetcher algorithm selection module further includes logic to adjust an accuracy ratio of the candidate prefetcher algorithm, compare the accuracy ratio with a threshold accuracy ratio, and determine whether to apply the first candidate prefetcher algorithm to the prefetcher module.

7. 发明申请

US20180196847A1 RECOGNITION OF FREE-FORM GESTURES FROM ORIENTATION TRACKING OF A HANDHELD OR WEARABLE DEVICE 审中-公开
公开(公告)号：US20180196847A1
公开(公告)日：2018-07-12
申请号：US15805042
申请日：2017-11-06
申请人： INTEL CORPORATION
发明人： Nicolas G. Mitri , Christopher B. Wilkerson , Mariette Awad
IPC分类号： G06F17/30 , G06F3/0487 , G06F1/16 , G06F3/01
CPC分类号： G06F17/30424 , G06F1/163 , G06F1/1694 , G06F3/011 , G06F3/017 , G06F3/0487 , G06F17/30312 , G06F17/30598
摘要： A user performs a gesture with a hand-held or wearable device capable of sensing its own orientation. Orientation data, in the form of a sequence of rotation vectors, is collected throughout the duration of the gesture. To construct a trace representing the shape of the gesture and the direction of device motion, the orientation data is processed by a robotic chain model with four or fewer degrees of freedom, simulating a set of joints moved by the user to perform the gesture (e.g., a shoulder and an elbow). To classify the gesture, a trace is compared to contents of a training database including many different users' versions of the gesture and analyzed by a learning module such as support vector machine.

8. 发明授权

US09594625B2 Sequential circuit with error detection 有权
标题翻译：具有错误检测的顺序电路
公开(公告)号：US09594625B2
公开(公告)日：2017-03-14
申请号：US14878985
申请日：2015-10-08
申请人： INTEL CORPORATION
发明人： Keith A. Bowman , James W. Tschanz , Nam Sung Kim , Janice C. Lee , Christopher B. Wilkerson , Shih-Lien L. Lu , Tanay Karnik , Vivek K. De
IPC分类号： G06F11/07 , G06F1/10 , H03K3/037 , G01R31/317
CPC分类号： G01R31/3177 , G01R31/31723 , G01R31/31725 , G01R31/31727 , G06F1/10 , G06F11/0706 , G06F11/0757 , G06F11/0793 , H03K3/0375
摘要： Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.
摘要翻译：提供了具有错误检测的顺序电路。例如，它们可以用于替代传统的主从触发器，例如在关键路径电路中，以检测并启动在顺序输入处的后期转换的校正。在一些实施例中，这样的顺序可以包括具有时间借用锁存器的转换检测器。

9. 发明授权

US09417879B2 Systems and methods for managing reconfigurable processor cores 有权
标题翻译：管理可重构处理器内核的系统和方法
公开(公告)号：US09417879B2
公开(公告)日：2016-08-16
申请号：US13924334
申请日：2013-06-21
申请人： Intel Corporation
发明人： Christopher B. Wilkerson , Alaa R. Alameldeen , Eugene Gorbatov , Zeshan A. Chishti
IPC分类号： G06F9/38 , G06F9/50
CPC分类号： G06F9/3836 , G06F9/5077 , G06F2209/507 , Y02D10/22 , Y02D10/36
摘要： Systems and methods for managing reconfigurable processor cores. An example processing system comprises a plurality of processor cores; a control register including a plurality of state bits, each state bit indicating a state of a corresponding processor core, the control register further including a plurality of inhibit bits, each inhibit bit indicating whether a corresponding processor core is allowed to merge with other processor cores; and a core management logic configured to merge a first processor core and a second processor core, responsive to determining that a first state bit corresponding to the first processor core is set, a first inhibit bit corresponding to the first processor core is cleared, a second state bit corresponding to the second processor core is cleared, and a second inhibit bit corresponding to the second processor core is cleared.
摘要翻译：管理可重构处理器内核的系统和方法。一个示例性处理系统包括多个处理器核心; 包括多个状态位的控制寄存器，每个状态位指示对应的处理器核心的状态，所述控制寄存器还包括多个禁止位，每个禁止位指示相应的处理器核心是否被允许与其他处理器核心合并 ; 以及核心管理逻辑，用于响应于确定与所述第一处理器核相对应的第一状态位被设置来合并第一处理器核和第二处理器核，清除与所述第一处理器核相对应的第一禁止位，对应于第二处理器核的状态位被清除，并且与第二处理器核相对应的第二禁止位被清除。

10. 发明授权

US10261901B2 Method and apparatus for unneeded block prediction in a computing system having a last level cache and a multi-level system memory 有权
公开(公告)号：US10261901B2
公开(公告)日：2019-04-16
申请号：US14865617
申请日：2015-09-25
申请人： INTEL CORPORATION
发明人： Zhe Wang , Christopher B. Wilkerson , Zeshan A. Chishti , Seth H. Pugsley , Alaa R. Alameldeen , Shih-Lien L. Lu
IPC分类号： G06F12/00 , G06F12/0811 , G06F3/06 , G06F12/0862 , G06F12/0888 , G06F12/0893 , G06F13/00 , G06F13/28
摘要： An apparatus is described. The apparatus includes a last level cache and a memory controller to interface to a multi-level system memory. The multi-level system memory has a caching level. The apparatus includes a first prediction unit to predict unneeded blocks in the last level cache. The apparatus includes a second prediction unit to predict unneeded blocks in the caching level of the multi-level system memory.

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