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1. 发明授权

US09245743B2 Methods for forming high-k dielectrics containing hafnium and zirconium using atomic layer deposition 有权
标题翻译：使用原子层沉积形成含有铪和锆的高k电介质的方法
公开(公告)号：US09245743B2
公开(公告)日：2016-01-26
申请号：US14109728
申请日：2013-12-17
申请人： Intermolecular Inc.
发明人： Khaled Ahmed , Frank Greer
IPC分类号： H01L21/02 , H01L29/51 , H01L21/28 , C23C16/40 , C23C16/455
CPC分类号： H01L21/02181 , C23C16/405 , C23C16/45531 , H01L21/02189 , H01L21/02194 , H01L21/0228 , H01L21/28194 , H01L29/513 , H01L29/517
摘要： Embodiments provided herein describe high-k dielectric layers and methods for forming high-k dielectric layers. A substrate is provided. The substrate includes a semiconductor material. The substrate is exposed to a hafnium precursor. The substrate is exposed to a zirconium precursor. The substrate is exposed to an oxidant only after the exposing of the substrate to the hafnium precursor and the exposing of the substrate to the zirconium precursor. The exposing of the substrate to the hafnium precursor, the exposing of the substrate to the zirconium precursor, and the exposing of the substrate to the oxidant causes a layer to be formed over the substrate. The layer includes hafnium, zirconium, and oxygen.
摘要翻译：本文提供的实施例描述了高k电介质层和用于形成高k电介质层的方法。提供基板。基板包括半导体材料。将基底暴露于铪前体。将基底暴露于锆前体。只有在将基底暴露于铪前体并将基底暴露于锆前体之后，才将基底暴露于氧化剂。将衬底暴露于铪前体，将衬底暴露于锆前体，以及将衬底暴露于氧化剂引起在衬底上形成一层。该层包括铪，锆和氧。

2. 发明申请

US20150041912A1 Gate Stacks Including TaXSiYO for MOSFETS 有权
标题翻译：包括用于MOSFET的TaXSiYO的栅极堆叠
公开(公告)号：US20150041912A1
公开(公告)日：2015-02-12
申请号：US14135381
申请日：2013-12-19
申请人： Intermolecular, Inc.
发明人： Khaled Ahmed , Frank Greer
IPC分类号： H01L21/28 , H01L27/092
CPC分类号： H01L21/28158 , H01L21/0215 , H01L21/0228 , H01L21/28255 , H01L21/28264 , H01L21/8258 , H01L27/092 , H01L29/16 , H01L29/20 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： Provided are field effect transistor (FET) assemblies and methods of forming thereof. An FET assembly may include a dielectric layer formed from tantalum silicon oxide and having the atomic ratio of silicon to tantalum and silicon (Si/(Ta+Si)) of less than 5% to provide a low trap density. The dielectric layer may be disposed over an interface layer, which is disposed over a channel region. The same type of the dielectric layer may be used a common gate dielectric of an nMOSFET (e.g., III-V materials) and a pMOSFET (e.g., germanium). The channel region may include one of indium gallium arsenide, indium phosphate, or germanium. The interface layer may include silicon oxide to provide a higher energy barrier. The dielectric layer may be formed using an atomic layer deposition technique by adsorbing both tantalum and silicon containing precursors on the deposition surface and then oxidizing both precursors in the same operation.
摘要翻译：提供场效应晶体管（FET）组件及其形成方法。 FET组件可以包括由钽氧化硅形成并且具有小于5％的硅与钽和硅（Si /（Ta + Si））的原子比的介电层以提供低陷阱密度。电介质层可以设置在界面层上，该界面层设置在沟道区域上。可以使用相同类型的电介质层的nMOSFET（例如，III-V材料）和pMOSFET（例如，锗）的公共栅极电介质。沟道区可以包括砷化铟镓，磷酸铟或锗中的一种。界面层可以包括氧化硅以提供更高的能量势垒。可以使用原子层沉积技术，通过在沉积表面上吸附含有钽和硅的两种前体，然后在相同的操作中氧化两种前体来形成电介质层。

3. 发明授权

US08901677B2 Nucleation interface for high-k layer on germanium 有权
标题翻译：锗上高k层的成核界面
公开(公告)号：US08901677B2
公开(公告)日：2014-12-02
申请号：US14198480
申请日：2014-03-05
申请人： Intermolecular, Inc.
发明人： Frank Greer , Edwin Adhiprakasha , Chi-I Lang , Ratsamee Limdulpaiboon , Sandip Niyogi , Kurt Pang , J. Watanabe
IPC分类号： H01L21/336 , H01L21/311 , H01L29/02
CPC分类号： H01L21/31122 , H01L21/02052 , H01L21/02236 , H01L21/02255 , H01L21/02301 , H01L21/02304 , H01L21/02312 , H01L21/02315 , H01L21/28255 , H01L29/02
摘要： A germanium-containing semiconductor surface is prepared for formation of a dielectric overlayer (e.g., a thin layer of high-k gate dielectric) by (1) removal of native oxide, for example by wet cleaning, (2) additional cleaning with hydrogen species, (3) in-situ formation of a controlled monolayer of GeO2, and (4) in-situ deposition of the dielectric overlayer to prevent uncontrolled regrowth of native oxide. The monolayer of GeO2 promotes uniform nucleation of the dielectric overlayer, but it too thin to appreciably impact the effective oxide thickness of the dielectric overlayer.
摘要翻译：制备含锗的半导体表面，用于通过（1）去除天然氧化物，例如通过湿法清洁来形成电介质覆盖层（例如，高k栅极电介质的薄层），（2）用氢物质进行额外的清洁，（3）原位形成受控单层的GeO 2，以及（4）电介质覆层的原位沉积，以防止天然氧化物的不受控制的再生长。 GeO2的单层促进电介质覆盖层的均匀成核，但它太薄而不能明显影响电介质覆盖层的有效氧化物厚度。

4. 发明授权

US09087864B2 Multipurpose combinatorial vapor phase deposition chamber 有权
标题翻译：多功能组合气相沉积室
公开(公告)号：US09087864B2
公开(公告)日：2015-07-21
申请号：US14135307
申请日：2013-12-19
申请人： Intermolecular, Inc.
发明人： Chen-An Chen , Tony P. Chiang , Frank Greer , Martin Romero , James Tsung
IPC分类号： H01L21/31 , H01L21/469 , H01L21/677 , H01L21/02
CPC分类号： H01L21/02271 , C23C16/04 , C23C16/45529 , C23C16/45544 , C23C16/45574 , C23C16/4584 , C23C16/54 , H01L21/02274 , H01L21/0228 , H01L21/6719 , H01L21/67207
摘要： In some embodiments, apparatus are provided that provide for flexible processing in high productivity combinatorial (HPC) system. The apparatus allow for interchangeable functionality that includes deposition, plasma treatment, ion beam treatment, in-situ annealing, and in-situ metrology. The apparatus are designed so that the functionality may be integrated within a single processing chamber for enhanced flexibility.
摘要翻译：在一些实施例中，提供了在高生产率组合（HPC）系统中提供灵活处理的装置。该装置允许可互换的功能，包括沉积，等离子体处理，离子束处理，原位退火和原位计量。该设备被设计为使得功能可以集成在单个处理室内以增强灵活性。

5. 发明申请

US20150179508A1 Tantalum-Based Copper Barriers and Methods for Forming the Same 审中-公开
标题翻译：钽基铜阻挡物及其形成方法
公开(公告)号：US20150179508A1
公开(公告)日：2015-06-25
申请号：US14138628
申请日：2013-12-23
申请人： INTERMOLECULAR INC.
发明人： Edwin Adhiprakasha , Sean Barstow , Frank Greer , Wenxian Zhu
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L21/76843 , H01L21/2855 , H01L21/28562 , H01L21/76846 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Embodiments described herein provide tantalum-based copper barriers and methods for forming such barriers. A dielectric body is provided. A first layer is formed above the dielectric body. The first layer includes tantalum. A second layer is formed above the first layer. The second layer includes manganese. A third layer is formed above the second layer. The third layer includes copper.
摘要翻译：本文所述的实施方案提供了钽基铜屏障和形成这种屏障的方法。提供介电体。第一层形成在绝缘体的上方。第一层包括钽。在第一层上方形成第二层。第二层包括锰。在第二层上方形成第三层。第三层包括铜。

6. 发明申请

US20150179438A1 GATE STACKS AND OHMIC CONTACTS FOR SIC DEVICES 有权
标题翻译：用于SIC设备的门盖和OHMIC联系
公开(公告)号：US20150179438A1
公开(公告)日：2015-06-25
申请号：US14136271
申请日：2013-12-20
申请人： Intermolecular, Inc.
发明人： Khaled Ahmed , Frank Greer , Raj Jammy
IPC分类号： H01L21/02 , H01L29/40
CPC分类号： H01L21/02301 , C23C16/0227 , C23C16/56 , H01L21/02164 , H01L21/02178 , H01L21/022 , H01L21/02274 , H01L21/0228 , H01L21/02307 , H01L21/02315 , H01L21/0234 , H01L21/0485 , H01L29/66068 , H01L29/78
摘要： SiC substrates are cleaned and provided to a process chamber. In-situ plasma surface treatments are applied to further clean the surface of the substrate. A dielectric interface layer is deposited in-situ to passivate the surface. Metal layers having a low work function are deposited above the dielectric interface layer. The stack is annealed at about 500C in forming gas to form low resistivity ohmic contacts to the SiC substrate. SiC substrates are cleaned and provided to a process chamber. In-situ plasma surface treatments are applied to further clean the surface of the substrate. A silicon oxide dielectric interface layer is deposited in-situ to passivate the surface. Optional plasma surface treatments are applied to further improve the performance of the silicon oxide dielectric interface layer. An aluminum oxide gate dielectric layer is deposited above the silicon oxide dielectric interface layer.
摘要翻译：将SiC衬底清洁并提供给处理室。施加原位等离子体表面处理以进一步清洁基底的表面。电介质界面层原位沉积以钝化表面。具有低功函数的金属层沉积在电介质界面层的上方。堆叠在大约500℃下在形成气体中退火以形成到SiC衬底的低电阻率欧姆接触。将SiC衬底清洁并提供给处理室。施加原位等离子体表面处理以进一步清洁基底的表面。氧化硅介电界面层原位沉积以钝化表面。施加可选的等离子体表面处理以进一步提高氧化硅介电界面层的性能。在氧化硅介电界面层上沉积氧化铝栅极电介质层。

7. 发明申请

US20150132938A1 Methods and Systems for Forming Reliable Gate Stack on Semiconductors 审中-公开
标题翻译：在半导体上形成可靠栅极叠层的方法和系统
公开(公告)号：US20150132938A1
公开(公告)日：2015-05-14
申请号：US14079410
申请日：2013-11-13
申请人： Intermolecular, Inc.
发明人： Khaled Ahmed , Frank Greer
IPC分类号： H01L29/51 , H01L21/28
CPC分类号： H01L29/517 , H01L21/28176 , H01L29/78
摘要： Methods are provided for the deposition of high-k gate dielectric materials which are doped with fluorine and/or nitrogen to improve the performance and reliability. The high-k dielectric materials may include at least one of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium aluminum oxide, titanium oxide, titanium silicon oxide, or titanium aluminum oxide. The fluorine dopant is provided from a layer including titanium nitride or amorphous silicon, where the layer is doped with at least one of fluorine or nitrogen. The dopants diffuse into the high-k dielectric material during a subsequent anneal process.
摘要翻译：提供了用于沉积掺杂有氟和/或氮的高k栅极电介质材料以提高性能和可靠性的方法。高k电介质材料可以包括氧化铪，氧化铪铪，氧化铪铝，氧化锆，氧化锆锆，氧化锆锆，氧化钛，氧化钛或氧化钛铝中的至少一种。氟掺杂剂由包括氮化钛或非晶硅的层提供，其中该层掺杂有氟或氮中的至少一种。在随后的退火过程中，掺杂剂扩散到高k电介质材料中。

8. 发明申请

US20150118828A1 Reduction of native oxides by annealing in reducing gas or plasma 有权
标题翻译：还原气体或等离子体中还原天然氧化物
公开(公告)号：US20150118828A1
公开(公告)日：2015-04-30
申请号：US14068906
申请日：2013-10-31
申请人： Intermolecular Inc.
发明人： Frank Greer , Amol Joshi , Kevin Kashefi , Albert Sanghyup Lee , Abhijit Pethe , J Watanabe
IPC分类号： H01L21/28 , H01L21/02
CPC分类号： H01L21/28158 , C23C16/0218 , C23C16/45525 , H01L21/02175 , H01L21/0228 , H01L21/28194 , H01L21/28238
摘要： Native oxide growth on germanium, silicon germanium, and InGaAs undesirably affects CET (capacitive equivalent thickness) and EOT (effective oxide thickness) of high-k and low-k metal-oxide layers formed on these semiconductors. Even if pre-existing native oxide is initially removed from the bare semiconductor surface, some metal oxide layers are oxygen-permeable in thicknesses below about 25 Å thick. Oxygen-containing species used in the metal-oxide deposition process may diffuse through these permeable layers, react with the underlying semiconductor, and re-grow the native oxide. To eliminate or mitigate this re-growth, the substrate is exposed to a gas or plasma reductant (e.g., containing hydrogen). The reductant diffuses through the permeable layers to react with the re-grown native oxide, detaching the oxygen and leaving the un-oxidized semiconductor. The reduction product(s) resulting from the reaction may then be removed from the substrate (e.g., driven off by heat).
摘要翻译：在锗，硅锗和InGaAs上的天然氧化物生长不利地影响在这些半导体上形成的高k和低k金属氧化物层的CET（电容等效厚度）和EOT（有效氧化物厚度）。即使预先存在的原生氧化物最初从裸露的半导体表面去除，一些金属氧化物层的厚度可以在大约25埃的厚度下透氧。在金属氧化物沉积工艺中使用的含氧物质可以扩散通过这些可渗透层，与下面的半导体反应，并重新生长天然氧化物。为了消除或减轻这种再生长，将基底暴露于气体或等离子体还原剂（例如含有氢气）中。还原剂通过可渗透层扩散以与再生的天然氧化物反应，分离氧并留下未氧化的半导体。然后可以从反应物中除去由反应产生的还原产物（例如，通过加热驱除）。

9. 发明授权

US08906709B1 Combinatorially variable etching of stacks including two dissimilar materials for etch pit density inspection 有权
标题翻译：组合可变蚀刻堆叠，包括用于蚀刻坑密度检查的两种不同材料
公开(公告)号：US08906709B1
公开(公告)日：2014-12-09
申请号：US14138797
申请日：2013-12-23
申请人： Intermolecular, Inc.
发明人： Khaled Ahmed , Frank Greer , George Mirth , Zhi-Wen Sun
IPC分类号： H01L21/66
CPC分类号： H01L22/12 , H01L21/6708 , H01L21/67253 , H01L22/20
摘要： Provided are methods of high productivity combinatorial (HPC) inspection of semiconductor substrates. A substrate includes two layers of dissimilar materials interfacing each other, such as a stack of a silicon bottom layer and an indium gallium arsenide top layer. The dissimilar materials have one or more of thermal, structural, and lattice mismatches. As a part of the inspection, the top layer is etched in a combinatorial manner. Specifically, the top layer is divided into multiple different site-isolated regions. One such region may be etched using different process conditions from another region. Specifically, etching temperature, etching duration and/or etchant composition may vary among the site-isolated regions. After combinatorial etching, each region is inspected to determine its etch-pit density (EPD) value. These values may be then analyzed to determine an overall EPD value for the substrate, which may involve discarding EPD values for over-etched and under-etched regions.
摘要翻译：提供了半导体衬底的高生产率组合（HPC）检验方法。衬底包括彼此相互接合的两层不同材料，例如硅底层和砷化铟镓顶层的叠层。不同材料具有热，结构和晶格失配中的一种或多种。作为检查的一部分，顶层以组合方式蚀刻。具体来说，顶层被分成多个不同的位置隔离区域。可以使用与另一区域不同的工艺条件来蚀刻一个这样的区域。具体地，蚀刻温度，蚀刻持续时间和/或蚀刻剂组成可以在位置隔离区域之间变化。在组合蚀刻之后，检查每个区域以确定其蚀刻坑密度（EPD）值。然后可以分析这些值以确定衬底的整体EPD值，这可能涉及丢弃过蚀刻和欠蚀刻区域的EPD值。

10. 发明授权

US09425376B2 Plasma cleaning of superconducting layers 有权
公开(公告)号：US09425376B2
公开(公告)日：2016-08-23
申请号：US14138672
申请日：2013-12-23
申请人： Intermolecular Inc.
发明人： Frank Greer , Andy Steinbach
IPC分类号： H01L39/24
CPC分类号： H01L39/2493
摘要： In a “window-junction” formation process for Josephson junction fabrication, a spacer dielectric is formed over the first superconducting electrode layer, then an opening (the “window” is formed to expose the part of the electrode layer to be used for the junction. In an atomic layer deposition (ALD) chamber (or multi-chamber sealed system) equipped with direct or remote plasma capability, the exposed part of the electrode is sputter-etched with Ar, H2, or a combination to remove native oxides, etch residues, and other contaminants. Optionally, an O2 or O3 pre-clean may precede the sputter etch. When the electrode is clean, the tunnel barrier layer is deposited by ALD in-situ without further oxidant exposure.

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