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1. 发明申请

US20170103817A1 MITIGATION SCHEME FOR SRAM FUNCTIONALITY 有权
公开(公告)号：US20170103817A1
公开(公告)日：2017-04-13
申请号：US14881718
申请日：2015-10-13
申请人： International Business Machines Corporation
发明人： Alan J. Drake , Rajiv V. Joshi
IPC分类号： G11C29/12 , G11C11/418 , G11C29/00 , G11C11/419
CPC分类号： G11C29/12 , G11C5/14 , G11C11/418 , G11C11/419 , G11C29/04 , G11C29/12005 , G11C29/1201 , G11C29/12015 , G11C29/16 , G11C29/24 , G11C29/50 , G11C29/50012 , G11C29/76 , G11C2029/1202 , G11C2029/1204 , G11C2029/5004
摘要： An system and method are configured to degrade a memory cell PFET voltage based on a sensor reading of a current operating point. This will enable additional control over the SRAM device, particularly during a write operation. In one embodiment, a system of SRAM memory devices is configured as a smart sensor with real-time corrective circuit action. The system and method samples write and read timing operations and is adaptable by performing real-time corrective action. The degrading of PFET voltage to reduce it strength and improve write characteristics include an implementation that includes a charge pump controllable for altering by decreasing a voltage applied to the PFET of a selected memory cell. In a further embodiment, an edge detector is built into the circuit that real-time assesses the strength of the memory write operation. In a further implementation, control logic functions as a Finite State Machine.

2. 发明申请

US20170102761A1 Multi-Core Dynamic Frequency Control System 审中-公开
公开(公告)号：US20170102761A1
公开(公告)日：2017-04-13
申请号：US14923908
申请日：2015-10-27
申请人： International Business Machines Corporation
发明人： Francesco A. Campisano , Alan J. Drake , Michael S. Floyd , David T. Hui , Pawel Owczarczyk , Marshall D. Tiner , Xiaobin Yuan
IPC分类号： G06F1/32
CPC分类号： G06F1/3206 , G06F1/08 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： An approach is provided in which a multi-core processor's first core determines whether it controls a system frequency that drives a group of cores included in the multi-core processor. When the first core is not controlling the system frequency for the group of cores, the first core uses an internal voltage control module to provide control information to the first core's programmable voltage regulator and, in turn, independently control the first core's voltage level. When the first core is controlling the system frequency, the first core receives voltage control information from pervasive control to control the first core's voltage levels.

3. 发明授权

US10156882B2 Multi-core dynamic frequency control system 有权
公开(公告)号：US10156882B2
公开(公告)日：2018-12-18
申请号：US14879269
申请日：2015-10-09
申请人： International Business Machines Corporation
发明人： Francesco A. Campisano , Alan J. Drake , Michael S. Floyd , David T. Hui , Pawel Owczarczyk , Marshall D. Tiner , Xiaobin Yuan
IPC分类号： G06F1/12 , G06F13/42 , H04L5/00 , H04L7/00 , G06F1/32 , G06F1/08
摘要： An approach is provided in which a multi-core processor's first core determines whether it controls a system frequency that drives a group of cores included in the multi-core processor. When the first core is not controlling the system frequency for the group of cores, the first core uses an internal voltage control module to provide control information to the first core's programmable voltage regulator and, in turn, independently control the first core's voltage level. When the first core is controlling the system frequency, the first core receives voltage control information from pervasive control to control the first core's voltage levels.

4. 发明授权

US09571100B2 Clock buffers with pulse drive capability for power efficiency 有权
标题翻译：具有脉冲驱动能力的时钟缓冲器，实现功率效率
公开(公告)号：US09571100B2
公开(公告)日：2017-02-14
申请号：US14973363
申请日：2015-12-17
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Aditya Bansal , Thomas J. Bucelot , Alan J. Drake , Phillip J. Restle , David W. Shan , Mrigank Sharad
IPC分类号： G06F1/04 , H03K19/00 , H03K3/012 , H03K5/05 , H03K5/13 , H03K5/06 , H03K5/135 , H03K5/00
CPC分类号： H03K19/0016 , H03K3/012 , H03K5/05 , H03K5/06 , H03K5/13 , H03K5/135 , H03K2005/00013 , H03K2005/00234
摘要： A clock driver is provided. The clock driver includes a multi-stage delay cell having an input, a positive pulse driving branch, a negative pulse driving branch, and an output. The input is for receiving an original version of a reference clock signal input to the clock driver and used to generate a global clock signal. The output is connected to the positive pulse driving branch and the negative pulse driving branch. The clock driver further includes a pulse generator having positive and negative pulse generator portions respectively connected to outputs of the positive and negative pulse driving branches. The pulse generator generates, at any given time, one of a positive pulse and a negative pulse responsive to a positive pulse enable signal and a negative pulse enable signal, respectively, and the original version of the reference clock signal input to the clock driver without modification.
摘要翻译：提供时钟驱动程序。时钟驱动器包括具有输入，正脉冲驱动分支，负脉冲驱动分支和输出的多级延迟单元。该输入用于接收输入到时钟驱动器的参考时钟信号的原始版本，并用于产生全局时钟信号。输出连接到正脉冲驱动分支和负脉冲驱动分支。时钟驱动器还包括脉冲发生器，其具有分别连接到正和负脉冲驱动分支的输出的正和负脉冲发生器部分。脉冲发生器在任何给定时间产生响应于正脉冲使能信号和负脉冲使能信号的正脉冲和负脉冲之一，以及输入到时钟驱动器的参考时钟信号的原始版本，而没有修改。

5. 发明授权

US09407247B2 Programmable delay circuit 有权
标题翻译：可编程延迟电路
公开(公告)号：US09407247B2
公开(公告)日：2016-08-02
申请号：US14520743
申请日：2014-10-22
申请人： International Business Machines Corporation
发明人： Alan J. Drake , Pawel Owczarczyk , Marshall D. Tiner , Xiaobin Yuan
IPC分类号： H03H11/26 , H03K5/13 , H03K5/135 , H03K5/00
CPC分类号： H03K5/133 , H03K5/131 , H03K5/135 , H03K2005/00058 , H03K2005/0015
摘要： A computing circuit that includes clocked circuitry, a controller, and a clock generator. The clocked circuitry is configured to receive data and to perform data manipulation on the data based on a first clock signal. The controller is configured to control the transmission of the data to the clocked circuitry. The clock generator is configured to receive as inputs a second clock signal and a delay control signal from the controller, and to delay the second clock signal to generate the first clock signal. The clock generator includes a main delay component configured to receive the second clock signal and to output the first clock signal. The clock generator also includes a switchable delay component connected in parallel with the main delay component, where the switchable delay component is configured to receive as an input the delay control signal from the controller.
摘要翻译：包括时钟电路，控制器和时钟发生器的计算电路。时钟电路被配置为基于第一时钟信号接收数据并对数据执行数据操作。控制器被配置为控制数据到时钟电路的传输。时钟发生器被配置为从控制器接收第二时钟信号和延迟控制信号作为输入，并且延迟第二时钟信号以产生第一时钟信号。时钟发生器包括被配置为接收第二时钟信号并输出第一时钟信号的主延迟部件。时钟发生器还包括与主延迟部件并联连接的可切换延迟部件，其中可切换延迟部件被配置为从控制器接收延迟控制信号作为输入。

6. 发明授权

US09276563B2 Clock buffers with pulse drive capability for power efficiency 有权
标题翻译：具有脉冲驱动能力的时钟缓冲器，实现功率效率
公开(公告)号：US09276563B2
公开(公告)日：2016-03-01
申请号：US14303671
申请日：2014-06-13
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Aditya Bansal , Thomas J. Bucelot , Alan J. Drake , Phillip J. Restle , David W. Shan , Mrigank Sharad
IPC分类号： G06F1/04 , H03K3/012 , H03K5/05 , H03K5/13 , H03K5/00
CPC分类号： H03K19/0016 , H03K3/012 , H03K5/05 , H03K5/06 , H03K5/13 , H03K5/135 , H03K2005/00013 , H03K2005/00234
摘要： A clock driver and corresponding method are provided. The clock driver includes a multi-stage delay cell having logic circuitry and a plurality of serially connected delay elements. An input of the delay elements receives an original version of a reference clock signal input to the clock driver and used to generate a global clock signal. An output of the delay elements connects to positive and negative pulse driving branches formed from the logic circuitry. The clock driver further includes a pulse generator forming positive and negative pulse generator portions respectively connected to outputs of the positive and negative pulse driving branches. The pulse generator generates, at any given time, one of a positive pulse and a negative pulse responsive to a positive pulse enable signal and a negative pulse enable signal, respectively, and the original version of the reference clock signal input to the clock driver without modification.
摘要翻译：提供了时钟驱动器和相应的方法。时钟驱动器包括具有逻辑电路和多个串行连接的延迟元件的多级延迟单元。延迟元件的输入接收输入到时钟驱动器的参考时钟信号的原始版本，并用于产生全局时钟信号。延迟元件的输出连接到由逻辑电路形成的正和负脉冲驱动分支。时钟驱动器还包括形成正和负脉冲发生器部分的脉冲发生器，分别连接到正和负脉冲驱动分支的输出。脉冲发生器在任何给定时间产生响应于正脉冲使能信号和负脉冲使能信号的正脉冲和负脉冲之一，以及输入到时钟驱动器的参考时钟信号的原始版本，而没有修改。

7. 发明申请

US20150081044A1 Dynamic Adjustment of Operational Parameters to Compensate for Sensor Based Measurements of Circuit Degradation 有权
公开(公告)号：US20150081044A1
公开(公告)日：2015-03-19
申请号：US14029060
申请日：2013-09-17
申请人： International Business Machines Corporation
发明人： Malcolm S. Allen-Ware , Alan J. Drake , Michael S. Floyd , Tilman Gloekler , Charles R. Lefurgy , Karthick Rajamani
IPC分类号： G05B13/02
CPC分类号： G05B13/024 , G06F11/008
摘要： A mechanism is provided for implementing an operational parameter change within the data processing system based on an identified degradation. One or more degradations existing in the data processing system are identified based on a set of degradation values obtained from a set of degradation sensors. A determination is made as to whether one or more operational parameters need to be modified based on the one or more identified degradations. Responsive to determining that the one or more operational parameters need to be modified based on the one or more identified degradations, an input change is implemented to a one or more control devices in order that the one or more operational parameters are modified.

8. 发明申请

US20140244212A1 Monitoring Aging of Silicon in an Integrated Circuit Device 有权
标题翻译：监测集成电路器件中硅的老化
公开(公告)号：US20140244212A1
公开(公告)日：2014-08-28
申请号：US13775502
申请日：2013-02-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Malcolm S. Allen-Ware , Ronald J. Bolam , Alan J. Drake , Charles R. Lefurgy , Barry P. Linder , Steven W. Mittl , Karthick Rajamani
IPC分类号： G01R31/28
CPC分类号： G01R31/2851
摘要： A mechanism is provided for determining a modeled age of a mufti-core processor. For each core in a set of cores in the multi-core processor, a determination is made of a temperature, a voltage, and a frequency at regular intervals for a set of degradations and a set of voltage domains, thereby forming the modeled age of the multi-core processor. A determination is made as to whether the modeled age of the multi-core processor is greater than an end-of-life value. Responsive to the modeled age of the multi-core processor being greater than an end-of-life value, an indication is sent that the multi-core processor requires replacement.
摘要翻译：提供了一种用于确定多核处理器的建模年龄的机制。对于多核处理器中的一组核心中的每个核心，确定一组降级和一组电压域的规则间隔的温度，电压和频率，从而形成建模年龄多核处理器。确定多核处理器的建模年龄是否大于寿命终止值。响应于多核处理器的建模年龄大于寿命终止值，发出多核处理器需要更换的指示。

9. 发明申请

US20140237302A1 CHARACTERIZATION AND FUNCTIONAL TEST IN A PROCESSOR OR SYSTEM UTILIZING CRITICAL PATH MONITOR TO DYNAMICALLY MANAGE OPERATIONAL TIMING MARGIN 有权
标题翻译：处理器或系统中的特征和功能测试使用关键路径监视器进行动态管理操作时序标记
公开(公告)号：US20140237302A1
公开(公告)日：2014-08-21
申请号：US13770447
申请日：2013-02-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Robert W. Berry, JR. , Alan J. Drake , Michael S. Floyd , Richard L. Willaman
IPC分类号： G06F11/34
CPC分类号： G06F11/3409 , G06F1/04 , G06F1/206 , G06F1/324 , G06F1/3243 , G06F11/24
摘要： Guardband validation for a device having a critical path monitor involves first applying multiple calibration settings to the monitor during functional operation of the processor, and recording corresponding guardbands which result in reduced timing margin. A desired guardband can later be selected for validation. The calibration settings can be based on delays for a critical path. A calibration test procedure can be used to determine the calibration delays for different operating frequencies or voltages that are set or, alternatively, the calibration delays can be set and resultant frequencies measured which are used to calculate the guardband amounts. The critical path monitor may include a modified calibration delay circuit which provides a calibrated delay signal to a critical path synthesis circuit, and the multiple calibration settings can be applied by changing delay taps of the calibration delay circuit in response to a bias delay signal from a power management controller.
摘要翻译：具有关键路径监视器的设备的保护带验证涉及在处理器的功能操作期间首先对监视器应用多个校准设置，并记录导致缩短定时裕度的对应保护带。可以选择所需的保护带进行验证。校准设置可以基于关键路径的延迟。可以使用校准测试程序来确定设置的不同工作频率或电压的校准延迟，或者替代地，可以设置校准延迟并且测量用于计算保护带量的合成频率。关键路径监视器可以包括修改的校准延迟电路，其向关键路径合成电路提供校准的延迟信号，并且可以通过响应于来自校准延迟电路的偏置延迟信号改变校准延迟电路的延迟抽头来应用多个校准设置电源管理控制器。

10. 发明申请

US20140223210A1 Tunable Sector Buffer for Wide Bandwidth Resonant Global Clock Distribution 有权
标题翻译：用于宽带宽共振全局时钟分配的可调谐扇区缓冲区
公开(公告)号：US20140223210A1
公开(公告)日：2014-08-07
申请号：US13759646
申请日：2013-02-05
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Thomas J. Bucelot , Alan J. Drake , Robert A. Groves , Jason D. Hibbeler , Yong I. Kim , Liang-Teck Pang , William R. Reohr , Phillip J. Restle , Michael G.R. Thomson
IPC分类号： G06F1/10 , G06F1/32
CPC分类号： G06F1/10 , G06F1/324 , Y02D10/126
摘要： A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit and a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid. The tunable sector buffer is configured to set latency and slew rate of the clock signal based on an identified resonant or non-resonant mode.
摘要翻译：宽带谐振时钟分布包括被配置为将时钟信号分配给集成电路的多个分量的时钟网格和被配置为接收时钟信号并向时钟网格提供输出的可调谐扇区缓冲器。可调谐扇区缓冲器被配置为基于所识别的谐振或非谐振模式来设置时钟信号的延迟和转换速率。

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