专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US10211324B2 Vertical p-type, n-type, p-type (PNP) junction integrated circuit (IC) structure 有权
公开(公告)号：US10211324B2
公开(公告)日：2019-02-19
申请号：US15795884
申请日：2017-10-27
申请人： International Business Machines Corporation
发明人： Joseph R. Greco , Qizhi Liu , Aaron L. Vallett , Robert F. Vatter
IPC分类号： H01L29/732 , H01L29/66 , H01L29/10 , H01L21/768 , H01L29/06 , H01L29/08 , H01L29/16 , H01L29/423 , H01L29/45 , H01L27/082 , H01L21/762 , H01L27/06 , H01L29/417 , H01L21/8249
摘要： Various particular embodiments include an integrated circuit (IC) structure having: a stack region; and a silicon substrate underlying and contacting the stack region, the silicon substrate including: a silicon region including a doped subcollector region; a set of isolation regions overlying the silicon region; a base region between the set of isolation regions and below the stack region, the base region including an intrinsic base contacting the stack region, an extrinsic base contacting the intrinsic base and the stack region, and an amorphized extrinsic base contact region contacting the extrinsic base; a collector region between the set of isolation regions; an undercut collector-base region between the set of isolation regions and below the base region; and a collector contact region contacting the collector region under the intrinsic base and the collector-base region via the doped subcollector region.

2. 发明申请

US20180069105A1 METHOD TO BUILD VERTICAL PNP IN A BICMOS TECHNOLOGY WITH IMPROVED SPEED 审中-公开
公开(公告)号：US20180069105A1
公开(公告)日：2018-03-08
申请号：US15795884
申请日：2017-10-27
申请人： International Business Machines Corporation
发明人： Joseph R. Greco , Qizhi Liu , Aaron L. Vallett , Robert F. Vatter
IPC分类号： H01L29/732 , H01L29/66 , H01L21/768 , H01L27/082 , H01L29/06 , H01L29/45 , H01L29/423 , H01L29/16 , H01L29/10 , H01L29/08 , H01L29/417 , H01L27/06 , H01L21/8249
CPC分类号： H01L29/732 , H01L21/76232 , H01L21/76879 , H01L21/8249 , H01L27/0623 , H01L27/0826 , H01L29/0649 , H01L29/0653 , H01L29/0804 , H01L29/0821 , H01L29/1004 , H01L29/16 , H01L29/41708 , H01L29/42304 , H01L29/456 , H01L29/66234 , H01L29/66272 , H01L29/66287
摘要： Various particular embodiments include an integrated circuit (IC) structure having: a stack region; and a silicon substrate underlying and contacting the stack region, the silicon substrate including: a silicon region including a doped subcollector region; a set of isolation regions overlying the silicon region; a base region between the set of isolation regions and below the stack region, the base region including an intrinsic base contacting the stack region, an extrinsic base contacting the intrinsic base and the stack region, and an amorphized extrinsic base contact region contacting the extrinsic base; a collector region between the set of isolation regions; an undercut collector-base region between the set of isolation regions and below the base region; and a collector contact region contacting the collector region under the intrinsic base and the collector-base region via the doped subcollector region.

3. 发明授权

US09324828B2 Vertical P-type, N-type, P-type (PNP) junction integrated circuit (IC) structure, and methods of forming 有权
标题翻译：垂直P型，N型，P型（PNP）结集成电路（IC）结构和成型方法
公开(公告)号：US09324828B2
公开(公告)日：2016-04-26
申请号：US14457524
申请日：2014-08-12
申请人： International Business Machines Corporation
发明人： Joseph R. Greco , Qizhi Liu , Aaron L. Vallett , Robert F. Vatter
IPC分类号： H01L21/331 , H01L29/66 , H01L29/732 , H01L29/10 , H01L21/768
CPC分类号： H01L29/732 , H01L21/76232 , H01L21/76879 , H01L21/8249 , H01L27/0623 , H01L27/0826 , H01L29/0649 , H01L29/0653 , H01L29/0804 , H01L29/0821 , H01L29/1004 , H01L29/16 , H01L29/41708 , H01L29/42304 , H01L29/456 , H01L29/66234 , H01L29/66272 , H01L29/66287
摘要： Various particular embodiments include a method of amorphizing a portion of silicon underneath the N+ base section of a PNP transistor structure. After amorphizing, the method can include selectively etching that implant-amorphized silicon to trim the collector-base area and collector-base junction. The selective etching is enhanced because the unimplanted silicon region etches at a distinct rate than the implant-amorphized silicon, allowing for control over the trimming of the collector-base junction.
摘要翻译：各种具体实施例包括使PNP晶体管结构的N +基极部分下方的硅的一部分非晶化的方法。在非晶化之后，该方法可以包括选择性地蚀刻该植入物非晶化硅以修整集电极 - 基极区域和集电极 - 基极结。选择性蚀刻被增强，因为未植入的硅区域以与植入物非晶化硅不同的速率蚀刻，允许控制集电极 - 基极结的修整。

4. 发明授权

US09837514B2 Vertical P-type, N-type, P-type (PNP) junction integrated circuit (IC) structure 有权
公开(公告)号：US09837514B2
公开(公告)日：2017-12-05
申请号：US15073763
申请日：2016-03-18
申请人： International Business Machines Corporation
发明人： Joseph R. Greco , Qizhi Liu , Aaron L. Vallett , Robert F. Vatter
IPC分类号： H01L29/73 , H01L29/732 , H01L29/66 , H01L29/10 , H01L21/768 , H01L29/06 , H01L29/08 , H01L29/16 , H01L29/423 , H01L29/45 , H01L27/082 , H01L27/06 , H01L29/417 , H01L21/8249
CPC分类号： H01L29/732 , H01L21/76232 , H01L21/76879 , H01L21/8249 , H01L27/0623 , H01L27/0826 , H01L29/0649 , H01L29/0653 , H01L29/0804 , H01L29/0821 , H01L29/1004 , H01L29/16 , H01L29/41708 , H01L29/42304 , H01L29/456 , H01L29/66234 , H01L29/66272 , H01L29/66287
摘要： Various particular embodiments include an integrated circuit (IC) structure having: a stack region; and a silicon substrate underlying and contacting the stack region, the silicon substrate including: a silicon region including a doped subcollector region; a set of isolation regions overlying the silicon region; a base region between the set of isolation regions and below the stack region, the base region including an intrinsic base contacting the stack region, an extrinsic base contacting the intrinsic base and the stack region, and an amorphized extrinsic base contact region contacting the extrinsic base; a collector region between the set of isolation regions; an undercut collector-base region between the set of isolation regions and below the base region; and a collector contact region contacting the collector region under the intrinsic base and the collector-base region via the doped subcollector region.

5. 发明授权

US09214318B1 Electromagnetic electron reflector 有权
标题翻译：电磁电子反射器
公开(公告)号：US09214318B1
公开(公告)日：2015-12-15
申请号：US14340744
申请日：2014-07-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Eric J. Caprarola , Robert C. Churchill , Joseph R. Greco , Nicholas Mone, Jr.
IPC分类号： H01J37/00 , H01J37/30 , H01J37/147 , H01J37/317
CPC分类号： H01J37/3171 , H01J37/026 , H01J2237/0042 , H01J2237/03
摘要： An electromagnetic electron reflector, an ion implanter having an electromagnetic reflector and a method of implantation using the ion implanter. The electromagnetic electron reflector includes a frame; permanent magnets within the frame; a center aperture within the frame and electrically isolated by first gaps from the frame and the permanent magnets and fixed in position by dielectric feed throughs, first cup shields integrally formed on the top and bottom edges of the center aperture, the dielectric feed throughs nested within the first cup shields; second cup shields integrally formed on inside surfaces of the top and bottom of the frame, the second cup shields nested within respective first cup shields; entrance and exit apertures attached to the frame and an electrical conductor passing through at least one of the dielectric feed throughs and electrically contacting the center aperture.
摘要翻译：电磁电子反射器，具有电磁反射器的离子注入机和使用离子注入机的注入方法。电磁电子反射器包括框架; 框架内的永磁体; 框架内的中心孔，并通过第一间隙从框架和永久磁铁隔离并通过介质馈通固定在适当的位置，第一杯形屏蔽件整体形成在中心孔的顶部和底部边缘上，电介质进料通过嵌套在内部第一杯盾牌; 第二杯罩一体地形成在框架的顶部和底部的内表面上，第二杯罩屏蔽嵌套在相应的第一杯罩内; 连接到框架的入口和出口孔以及穿过至少一个电介质进料通道并与中心孔电接触的电导体。

6. 发明申请

US20160049492A1 VERTICAL P-TYPE, N-TYPE, P-TYPE (PNP) JUNCTION INTEGRATED CIRCUIT (IC) STRUCTURE, AND METHODS OF FORMING 有权
标题翻译：垂直P型，N型，P型（PNP）结集成电路（IC）结构及其形成方法
公开(公告)号：US20160049492A1
公开(公告)日：2016-02-18
申请号：US14457524
申请日：2014-08-12
申请人： International Business Machines Corporation
发明人： Joseph R. Greco , Qizhi Liu , Aaron L. Vallett , Robert F. Vatter
IPC分类号： H01L29/66 , H01L29/10 , H01L21/768 , H01L29/732
CPC分类号： H01L29/732 , H01L21/76232 , H01L21/76879 , H01L21/8249 , H01L27/0623 , H01L27/0826 , H01L29/0649 , H01L29/0653 , H01L29/0804 , H01L29/0821 , H01L29/1004 , H01L29/16 , H01L29/41708 , H01L29/42304 , H01L29/456 , H01L29/66234 , H01L29/66272 , H01L29/66287
摘要： Various particular embodiments include a method of amorphizing a portion of silicon underneath the N+ base section of a PNP transistor structure. After amorphizing, the method can include selectively etching that implant-amorphized silicon to trim the collector-base area and collector-base junction. The selective etching is enhanced because the unimplanted silicon region etches at a distinct rate than the implant-amorphized silicon, allowing for control over the trimming of the collector-base junction.
摘要翻译：各种具体实施例包括使PNP晶体管结构的N +基极部分下方的硅的一部分非晶化的方法。在非晶化之后，该方法可以包括选择性地蚀刻该植入物非晶化硅以修整集电极 - 基极区域和集电极 - 基极结。选择性蚀刻被增强，因为未植入的硅区域以与植入物非晶化硅不同的速率蚀刻，允许控制集电极 - 基极结的修整。

7. 发明授权

US09735259B2 Method to build vertical PNP in a BiCMOS technology with improved speed 有权
公开(公告)号：US09735259B2
公开(公告)日：2017-08-15
申请号：US14834699
申请日：2015-08-25
申请人： International Business Machines Corporation
发明人： Joseph R. Greco , Qizhi Liu , Aaron L. Vallett , Robert F. Vatter
IPC分类号： H01L29/73 , H01L29/732 , H01L29/66 , H01L29/10 , H01L21/768 , H01L29/06 , H01L29/08 , H01L29/16 , H01L29/423 , H01L29/45 , H01L27/082 , H01L27/06 , H01L29/417 , H01L21/8249
CPC分类号： H01L29/732 , H01L21/76232 , H01L21/76879 , H01L21/8249 , H01L27/0623 , H01L27/0826 , H01L29/0649 , H01L29/0653 , H01L29/0804 , H01L29/0821 , H01L29/1004 , H01L29/16 , H01L29/41708 , H01L29/42304 , H01L29/456 , H01L29/66234 , H01L29/66272 , H01L29/66287
摘要： Various particular embodiments include an integrated circuit (IC) structure including: a stack region; and a silicon substrate underlying and contacting the stack region, the silicon substrate including: a silicon region including a doped subcollector region; a set of isolation regions overlying the silicon region; a base region between the set of isolation regions and below the stack region, the base region including an intrinsic base contacting the stack region, an extrinsic base contacting the intrinsic base and the stack region, and an amorphized extrinsic base contact region contacting the extrinsic base; a collector region between the set of isolation regions; an undercut collector-base region between the set of isolation regions and below the base region; and a collector contact region contacting the collector region under the intrinsic base and the collector-base region via the doped subcollector region.

8. 发明申请

US20160197167A1 Vertical P-Type, N-Type, P-Type (PNP) Junction Integrated Circuit (IC) Structure 有权
标题翻译：垂直P型，N型，P型（PNP）结集成电路（IC）结构
公开(公告)号：US20160197167A1
公开(公告)日：2016-07-07
申请号：US15073763
申请日：2016-03-18
申请人： International Business Machines Corporation
发明人： Joseph R. Greco , Qizhi Liu , Aaron L. Vallett , Robert F. Vatter
IPC分类号： H01L29/732 , H01L29/10 , H01L29/423 , H01L29/45 , H01L27/06 , H01L29/06 , H01L29/08
CPC分类号： H01L29/732 , H01L21/76232 , H01L21/76879 , H01L21/8249 , H01L27/0623 , H01L27/0826 , H01L29/0649 , H01L29/0653 , H01L29/0804 , H01L29/0821 , H01L29/1004 , H01L29/16 , H01L29/41708 , H01L29/42304 , H01L29/456 , H01L29/66234 , H01L29/66272 , H01L29/66287
摘要： Various particular embodiments include an integrated circuit (IC) structure having: a stack region; and a silicon substrate underlying and contacting the stack region, the silicon substrate including: a silicon region including a doped subcollector region; a set of isolation regions overlying the silicon region; a base region between the set of isolation regions and below the stack region, the base region including an intrinsic base contacting the stack region, an extrinsic base contacting the intrinsic base and the stack region, and an amorphized extrinsic base contact region contacting the extrinsic base; a collector region between the set of isolation regions; an undercut collector-base region between the set of isolation regions and below the base region; and a collector contact region contacting the collector region under the intrinsic base and the collector-base region via the doped subcollector region.
摘要翻译：各种具体实施例包括具有堆叠区域的集成电路（IC）结构; 以及位于所述堆叠区域下方并接触的硅衬底，所述硅衬底包括：包含掺杂子集电极区域的硅区域; 一组覆盖硅区的隔离区; 所述基极区域在所述隔离区域之间并且在所述堆叠区域之下，所述基极区域包括与所述堆叠区域接触的本征基极，与所述本征基极和所述堆叠区域接触的非本征基极，以及接触所述外部基极的非晶化非本征基极接触区域 ; 在所述一组隔离区域之间的集电极区域; 在所述一组隔离区域和所述基底区域之下的底切集电极 - 基极区域; 以及通过掺杂子集电极区域与本征基极之下的集电极区域和集电极 - 基极区域接触的集电极接触区域。

9. 发明申请

US20160049501A1 Method to build vertical PNP in a BICMOS technology with improved speed 有权
标题翻译：在BICMOS技术中建立垂直PNP的方法，提高速度
公开(公告)号：US20160049501A1
公开(公告)日：2016-02-18
申请号：US14834699
申请日：2015-08-25
申请人： International Business Machines Corporation
发明人： Joseph R. Greco , Qizhi Liu , Aaron L. Vallett , Robert F. Vatter
IPC分类号： H01L29/732 , H01L29/16 , H01L29/06 , H01L27/06 , H01L29/08 , H01L29/417 , H01L29/423 , H01L29/45 , H01L29/10
CPC分类号： H01L29/732 , H01L21/76232 , H01L21/76879 , H01L21/8249 , H01L27/0623 , H01L27/0826 , H01L29/0649 , H01L29/0653 , H01L29/0804 , H01L29/0821 , H01L29/1004 , H01L29/16 , H01L29/41708 , H01L29/42304 , H01L29/456 , H01L29/66234 , H01L29/66272 , H01L29/66287
摘要： Various particular embodiments include an integrated circuit (IC) structure including: a stack region; and a silicon substrate underlying and contacting the stack region, the silicon substrate including: a silicon region including a doped subcollector region; a set of isolation regions overlying the silicon region; a base region between the set of isolation regions and below the stack region, the base region including an intrinsic base contacting the stack region, an extrinsic base contacting the intrinsic base and the stack region, and an amorphized extrinsic base contact region contacting the extrinsic base; a collector region between the set of isolation regions; an undercut collector-base region between the set of isolation regions and below the base region; and a collector contact region contacting the collector region under the intrinsic base and the collector-base region via the doped subcollector region.
摘要翻译：各种具体实施例包括集成电路（IC）结构，包括：堆叠区域; 以及位于所述堆叠区域下方并接触的硅衬底，所述硅衬底包括：包含掺杂子集电极区域的硅区域; 一组覆盖硅区的隔离区; 所述基极区域在所述隔离区域之间并且在所述堆叠区域之下，所述基极区域包括与所述堆叠区域接触的本征基极，与所述本征基极和所述堆叠区域接触的非本征基极，以及接触所述外部基极的非晶化非本征基极接触区域 ; 在所述一组隔离区域之间的集电极区域; 在所述一组隔离区域和所述基底区域之下的底切集电极 - 基极区域; 以及通过掺杂子集电极区域与本征基极之下的集电极区域和集电极 - 基极区域接触的集电极接触区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式