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1. 发明授权

US09710577B2 Heat source integration for electromigration analysis 有权
公开(公告)号：US09710577B2
公开(公告)日：2017-07-18
申请号：US14877189
申请日：2015-10-07
申请人： International Business Machines Corporation
发明人： Steven J. Baumgartner , James M. Johnson , David M. Onsongo
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F2217/76 , G06F2217/80
摘要： A computer-implemented method includes receiving layout information associated with a circuit design at an extractor, and generating three-dimensional (3-D) heat source grid information based on the layout information, an extracted netlist, and wire information. The method also includes sending the wire information to an electromigration(EM)/current(IR) analyzer, sending the extracted netlist to a circuit simulator, and sending the 3-D heat source grid information to a thermal analysis component. The circuit simulator is configured to generate temperature waveforms and current waveforms based on the extracted netlist. The thermal analysis component is configured to generate heat source information to be provided to the EM/IR analyzer. The method further includes determining, at the EM/IR analyzer, an electromigration risk associated with a wire based on the wire information, the current waveforms, and the heat source information.

2. 发明授权

US09712170B2 Level-shifting latch 有权
公开(公告)号：US09712170B2
公开(公告)日：2017-07-18
申请号：US14582396
申请日：2014-12-24
申请人： International Business Machines Corporation
发明人： Anthony G. Aipperspach , Steven J. Baumgartner , Charles P. Geer , David P. Paulsen , David W. Siljenberg , Alan P. Wagstaff
IPC分类号： H03K19/0175 , H03K19/094 , H03K19/0185 , G06F17/50
CPC分类号： H03K19/018521 , G06F17/505
摘要： A level-shifting latch circuit for coupling a first circuit in a first voltage domain with a second circuit in a second voltage domain, includes an input node to receive an input signal provided by the first circuit, and an output node to output a level-shifted signal, corresponding with the input signal. The level-shifting latch circuit also includes a first latch, having a first node and a second node, for storing the input signal in the first voltage domain, and a second latch, having a third node and a fourth node, for storing the input signal in the second voltage domain. In addition, the level-shifting circuit also includes a first switching element which provides a path to transfer a low voltage at the first node to the third node, and a second switching element which provides a path to transfer a low voltage at the second node to the fourth node.

3. 发明授权

US09553584B2 Level-shifting latch 有权
标题翻译：电平转换锁存器
公开(公告)号：US09553584B2
公开(公告)日：2017-01-24
申请号：US14580480
申请日：2014-12-23
申请人： International Business Machines Corporation
发明人： Anthony G. Aipperspach , Steven J. Baumgartner , Charles P. Geer , David P. Paulsen , David W. Siljenberg , Alan P. Wagstaff
IPC分类号： H03K19/0175 , H03K19/0185 , G06F17/50
CPC分类号： H03K19/018521 , G06F17/505
摘要： A level-shifting latch circuit for coupling a first circuit in a first voltage domain with a second circuit in a second voltage domain, includes an input node to receive an input signal provided by the first circuit, and an output node to output a level-shifted signal, corresponding with the input signal. The level-shifting latch circuit also includes a first latch, having a first node and a second node, for storing the input signal in the first voltage domain, and a second latch, having a third node and a fourth node, for storing the input signal in the second voltage domain. In addition, the level-shifting circuit also includes a first switching element which provides a path to transfer a low voltage at the first node to the third node, and a second switching element which provides a path to transfer a low voltage at the second node to the fourth node.
摘要翻译：用于将第一电压域中的第一电路与第二电压域中的第二电路耦合的电平转换锁存电路包括用于接收由第一电路提供的输入信号的输入节点和输出节点，移位信号，与输入信号对应。电平移位锁存电路还包括具有第一节点和第二节点的第一锁存器，用于将输入信号存储在第一电压域中，第二锁存器具有第三节点和第四节点，用于存储输入信号在第二电压域。此外，电平移位电路还包括第一开关元件，其提供将第一节点处的低电压传送到第三节点的路径;以及第二开关元件，其提供在第二节点处传送低电压的路径到第四个节点。

4. 发明授权

US09474034B1 Power reduction in a parallel data communications interface using clock resynchronization 有权
标题翻译：并行数据通信接口中的功耗降低，使用时钟重新同步
公开(公告)号：US09474034B1
公开(公告)日：2016-10-18
申请号：US14954418
申请日：2015-11-30
申请人： International Business Machines Corporation
发明人： Steven J. Baumgartner , Daniel M. Dreps , Michael B. Spear
IPC分类号： H04W56/00 , H04W24/08
CPC分类号： G06F1/3253 , G06F1/3206 , G06F1/3287 , H04L7/08 , H04W24/08 , H04W56/001 , Y02D70/00
摘要： A digital data communications mechanism includes multiple parallel lines, in which components of one or more lines are temporarily powered down to save power. Preferably, both the transmitter and receiver contain respective generators generating identical pre-determined pseudo-random bit streams, which are initially synchronized and which remain powered up when the line is temporarily powered down. Upon re-powering the line, the transmitter transmits the locally generated bit stream, and the receiver compares the received bit stream with its internally generated bit stream to determine an amount of shift required for re-synchronization.
摘要翻译：数字数据通信机构包括多条并行线路，其中一条或多条线路的组件被暂时断电以节省功率。优选地，发射机和接收机都包含相应的生成器，其生成相同的预定义伪随机比特流，它们最初是同步的，并且当线路暂时断电时保持加电。在重新为线路供电时，发射机发送本地生成的比特流，并且接收机将接收到的比特流与其内部生成的比特流进行比较，以确定重新同步所需的移位量。

5. 发明申请

US20160182053A1 LEVEL-SHIFTING LATCH 有权
公开(公告)号：US20160182053A1
公开(公告)日：2016-06-23
申请号：US14582396
申请日：2014-12-24
申请人： International Business Machines Corporation
发明人： Anthony G. Aipperspach , Steven J. Baumgartner , Charles P. Geer , David P. Paulsen , David W. Siljenberg , Alan P. Wagstaff
IPC分类号： H03K19/0185 , G06F17/50
CPC分类号： H03K19/018521 , G06F17/505
摘要： A level-shifting latch circuit for coupling a first circuit in a first voltage domain with a second circuit in a second voltage domain, includes an input node to receive an input signal provided by the first circuit, and an output node to output a level-shifted signal, corresponding with the input signal. The level-shifting latch circuit also includes a first latch, having a first node and a second node, for storing the input signal in the first voltage domain, and a second latch, having a third node and a fourth node, for storing the input signal in the second voltage domain. In addition, the level-shifting circuit also includes a first switching element which provides a path to transfer a low voltage at the first node to the third node, and a second switching element which provides a path to transfer a low voltage at the second node to the fourth node.

6. 发明申请

US20160182052A1 LEVEL-SHIFTING LATCH 有权
标题翻译：水平移位锁
公开(公告)号：US20160182052A1
公开(公告)日：2016-06-23
申请号：US14580480
申请日：2014-12-23
申请人： International Business Machines Corporation
发明人： Anthony G. Aipperspach , Steven J. Baumgartner , Charles P. Geer , David P. Paulsen , David W. Siljenberg , Alan P. Wagstaff
IPC分类号： H03K19/0185
CPC分类号： H03K19/018521 , G06F17/505
摘要： A level-shifting latch circuit for coupling a first circuit in a first voltage domain with a second circuit in a second voltage domain, includes an input node to receive an input signal provided by the first circuit, and an output node to output a level-shifted signal, corresponding with the input signal. The level-shifting latch circuit also includes a first latch, having a first node and a second node, for storing the input signal in the first voltage domain, and a second latch, having a third node and a fourth node, for storing the input signal in the second voltage domain. In addition, the level-shifting circuit also includes a first switching element which provides a path to transfer a low voltage at the first node to the third node, and a second switching element which provides a path to transfer a low voltage at the second node to the fourth node.
摘要翻译：用于将第一电压域中的第一电路与第二电压域中的第二电路耦合的电平转换锁存电路包括用于接收由第一电路提供的输入信号的输入节点和输出节点，移位信号，与输入信号对应。电平移位锁存电路还包括具有第一节点和第二节点的第一锁存器，用于将输入信号存储在第一电压域中，第二锁存器具有第三节点和第四节点，用于存储输入信号在第二电压域。此外，电平移位电路还包括第一开关元件，其提供将第一节点处的低电压传送到第三节点的路径;以及第二开关元件，其提供在第二节点处传送低电压的路径到第四个节点。

7. 发明授权

US09715270B2 Power reduction in a parallel data communications interface using clock resynchronization 有权
公开(公告)号：US09715270B2
公开(公告)日：2017-07-25
申请号：US15040979
申请日：2016-02-10
申请人： International Business Machines Corporation
发明人： Steven J. Baumgartner , Daniel M. Dreps , Michael B. Spear
IPC分类号： H04W56/00 , G06F1/32 , H04L7/08
CPC分类号： G06F1/3253 , G06F1/3206 , G06F1/3287 , H04L7/08 , H04W24/08 , H04W56/001 , Y02D70/00
摘要： A digital data communications mechanism includes multiple parallel lines, in which components of one or more lines are temporarily powered down to save power. Preferably, both the transmitter and receiver contain respective generators generating identical pre-determined pseudo-random bit streams, which are initially synchronized and which remain powered up when the line is temporarily powered down. Upon re-powering the line, the transmitter transmits the locally generated bit stream, and the receiver compares the received bit stream with its internally generated bit stream to determine an amount of shift required for re-synchronization.

8. 发明申请

US20170153689A1 Power Reduction in a Parallel Data Communications Interface Using Clock Resynchronization 有权
公开(公告)号：US20170153689A1
公开(公告)日：2017-06-01
申请号：US15040979
申请日：2016-02-10
申请人： International Business Machines Corporation
发明人： Steven J. Baumgartner , Daniel M. Dreps , Michael B. Spear
IPC分类号： G06F1/32 , H04L7/08
CPC分类号： G06F1/3253 , G06F1/3206 , G06F1/3287 , H04L7/08 , H04W24/08 , H04W56/001 , Y02D70/00
摘要： A digital data communications mechanism includes multiple parallel lines, in which components of one or more lines are temporarily powered down to save power. Preferably, both the transmitter and receiver contain respective generators generating identical pre-determined pseudo-random bit streams, which are initially synchronized and which remain powered up when the line is temporarily powered down. Upon re-powering the line, the transmitter transmits the locally generated bit stream, and the receiver compares the received bit stream with its internally generated bit stream to determine an amount of shift required for re-synchronization.

9. 发明申请

US20170103146A1 HEAT SOURCE INTEGRATION FOR ELECTROMIGRATION ANALYSIS 有权
公开(公告)号：US20170103146A1
公开(公告)日：2017-04-13
申请号：US14877189
申请日：2015-10-07
申请人： International Business Machines Corporation
发明人： Steven J. Baumgartner , James M. Johnson , David M. Onsongo
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F2217/76 , G06F2217/80
摘要： A computer-implemented method includes receiving layout information associated with a circuit design at an extractor, and generating three-dimensional (3-D) heat source grid information based on the layout information, an extracted netlist, and wire information. The method also includes sending the wire information to an electromigration(EM)/current(IR) analyzer, sending the extracted netlist to a circuit simulator, and sending the 3-D heat source grid information to a thermal analysis component. The circuit simulator is configured to generate temperature waveforms and current waveforms based on the extracted netlist. The thermal analysis component is configured to generate heat source information to be provided to the EM/IR analyzer. The method further includes determining, at the EM/IR analyzer, an electromigration risk associated with a wire based on the wire information, the current waveforms, and the heat source information.

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