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1. 发明授权

US09952651B2 Deterministic current based frequency optimization of processor chip 有权
公开(公告)号：US09952651B2
公开(公告)日：2018-04-24
申请号：US14814870
申请日：2015-07-31
申请人： International Business Machines Corporation
发明人： Malcolm S. Allen-Ware , Michael S. Floyd , Joshua D. Friedrich , Charles R. Lefurgy , Kirk D. Peterson , Karthick Rajamani , Srinivasan Ramani , Todd J. Rosedahl , Gregory S. Still , Brian W. Thompto , Victor Zyuban
IPC分类号： G06F1/00 , G06F1/32
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3206 , G06F1/3243 , Y02D10/126 , Y02D10/152
摘要： A system for adjusting a frequency of a processor is disclosed herein. The system includes a processor and a memory, where the memory includes a program configured to adjust a frequency of a multi-core processor. The operations include determining a total current and a temperature of the multi-core processor and estimating a leakage current for the multi-core processor. The operations also include calculating a switching current by subtracting the leakage current from the total current and calculating an effective switching capacitance based at least in part on the switching current. The operations also include calculating a workload activity factor by dividing the effective switching capacitance by a predetermined effective switching capacitance stored in vital product data, and enforcing a turbo frequency limit of the multi-core processor based on the workload activity factor.

2. 发明授权

US09323302B2 Rotating voltage control 有权
标题翻译：旋转电压控制
公开(公告)号：US09323302B2
公开(公告)日：2016-04-26
申请号：US14134428
申请日：2013-12-19
申请人： International Business Machines Corporation
发明人： Pradip Bose , Alper Buyuktosunoglu , Hans M. Jacobson , Victor Zyuban
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/26 , G06F1/3296 , Y02D10/172
摘要： According to one embodiment, a system is provided that includes at least one power gated component and two or more power switch transistors configured to provide one or more conductive paths between a common power supply rail, the at least one power gated component, and a ground. The two or more power switch transistors each include a source terminal, a drain terminal, and a gate terminal configured to control current flow between the source and drain terminals. The system also includes a rotating voltage control coupled to the gate terminals and configured to apply a sequence of control signals rotating between an on-state and an off-state to each of the gate terminals while the at least one power gated component is turned on. A switch activation ratio level is programmable to set a number of power switch transistors in the on-state relative to a total number of power switch transistors.
摘要翻译：根据一个实施例，提供了一种系统，其包括至少一个电力选通部件和两个或更多个功率开关晶体管，其被配置为在公共供电轨道，至少一个电力门控部件和地面之间提供一个或多个导电路径。两个或更多个功率开关晶体管每个包括源极端子，漏极端子和被配置为控制源极和漏极端子之间的电流的栅极端子。该系统还包括耦合到栅极端子的旋转电压控制，并且被配置为在至少一个电力门控部件被接通的同时，将在导通状态和截止状态之间旋转的一系列控制信号施加到每个栅极端子。开关激活比电平是可编程的，以将多个功率开关晶体管相对于功率开关晶体管的总数设置为导通状态。

3. 发明申请

US20150162904A1 EFFICIENT WAKEUP OF POWER GATED DOMAINS THROUGH CHARGE SHARING AND RECYCLING 审中-公开
标题翻译：通过充电分享和回收，高效地唤醒电力门控域
公开(公告)号：US20150162904A1
公开(公告)日：2015-06-11
申请号：US14624026
申请日：2015-02-17
申请人： International Business Machines Corporation
发明人： Pradip Bose , Alper Buyuktosunoglu , Hans Jacobson , Victor Zyuban
IPC分类号： H03K17/51
CPC分类号： H03K3/012 , H02J1/00 , H02J1/14 , H03K3/0375 , H03K17/22 , H03K17/51 , Y10T307/469
摘要： A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any circuits to a common voltage source. A powered off circuit is disconnected from the common voltage source. A first capacitor and a second capacitor are configured to supply wakeup electrical charge to a given circuit of the circuits. The first capacitor and the second capacitor are connectable to the given circuit and the powered off circuit. A controller is configured to controllably connect the first capacitor and/or the second capacitor to the given circuit in order to supply the wakeup electrical charge to the given circuit, when the powered off circuit was previously connected to the first capacitor and/or the second capacitor.
摘要翻译：为具有电源门控的集成电路提供了一种机制。电源开关被配置为连接和断开任何电路到公共电压源。断电电路与公共电压源断开。第一电容器和第二电容器被配置为向电路的给定电路提供唤醒电荷。第一电容器和第二电容器可连接到给定电路和断电电路。控制器被配置为可控地将第一电容器和/或第二电容器连接到给定电路，以便当断电电路预先连接到第一电容器和/或第二电容器时将唤醒电荷提供给给定电路电容器。

4. 发明申请

US20150082069A1 ACCELERATING MICROPROCESSOR CORE WAKE UP VIA CHARGE FROM CAPACITANCE TANK WITHOUT INTRODUCING NOISE ON POWER GRID OF RUNNING MICROPROCESSOR CORES 有权
公开(公告)号：US20150082069A1
公开(公告)日：2015-03-19
申请号：US14026444
申请日：2013-09-13
申请人： International Business Machines Corporation
发明人： Pradip Bose , Alper Buyuktosunoglu , Hans Jacobson , Victor Zyuban
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/26 , Y02D10/171
摘要： A mechanism is provided for an integrated circuit with power gating. A power switch is configured to connect and disconnect circuits to a common voltage source. A capacitor tank is configured to supply wakeup charge to a given circuit. A controllable element is connected to the given circuit and to the capacitor tank. The controllable element is configured to controllably connect and disconnect the capacitor tank to the given circuit in order to supply the wakeup charge to the given circuit. The controllable element is configured to, responsive to the power switch disconnecting the given circuit from the common voltage source and to the given circuit being turned on to wakeup, supply the wakeup charge to the given circuit being turned on by transferring the wakeup charge from the capacitor tank to the given circuit. This reduces the electrical charge transferred from the circuits connected to the common voltage source.

5. 发明申请

US20150082066A1 ACCELERATING THE MICROPROCESSOR CORE WAKEUP BY PREDICTIVELY EXECUTING A SUBSET OF THE POWER-UP SEQUENCE 有权
标题翻译：通过预先执行上电序列的方式加快微处理器芯片唤醒
公开(公告)号：US20150082066A1
公开(公告)日：2015-03-19
申请号：US14171899
申请日：2014-02-04
申请人： International Business Machines Corporation
发明人： Pradip Bose , Alper Buyuktosunoglu , Hans Jacobson , Victor Zyuban
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/26 , Y02D10/171 , Y02D50/20
摘要： A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any one of multiple circuits to a common voltage source, where a powered off circuit is disconnected from the common voltage source. A power-up sequencer includes an initial stages power-up component and a final stages power-up component. The final stages power-up component is configured to execute final stages of a power-up process for the powered off circuit, and the initial stages power-up component is configured to execute initial stages of the power-up process for the powered off circuit. The initial stages power-up component is activated in response to a predictive power-up request.
摘要翻译：为具有电源门控的集成电路提供了一种机制。电源接头开关被配置为将多个电路中的任何一个连接到一个公共电压源，其中断电电路与公共电压源断开。上电序列器包括初始阶段上电组件和最后阶段上电组件。最后阶段上电组件被配置为执行关闭电路的上电过程的最后阶段，并且初始阶段上电组件被配置为执行关断电路的上电过程的初始阶段。响应于预测的上电请求，初始级上电组件被激活。

6. 发明授权

US09971393B2 Dynamic workload frequency optimization 有权
公开(公告)号：US09971393B2
公开(公告)日：2018-05-15
申请号：US14970716
申请日：2015-12-16
申请人： International Business Machines Corporation
发明人： Bjorn P. Christensen , Victor Zyuban
IPC分类号： G06F1/32 , G06F9/30
CPC分类号： G06F1/3243 , G06F1/324 , G06F9/30145
摘要： The embodiments described herein relate to dynamically detecting a frequency change condition for microprocessor performance. An instruction is received, and a frequency change condition associated with the received instruction is dynamically detected. A frequency modulation is performed in response to the dynamic detection. The frequency modulation includes selecting a second frequency for optimal instruction processing different from a first frequency, the first frequency being a default operating frequency of the microprocessor. Execution of the instruction is completed at the second frequency. Accordingly, incoming execution instructions are logically analyzed, and the processor frequency is selectively modified based on associated instruction conditions.

7. 发明授权

US09298253B2 Accelerating the microprocessor core wakeup by predictively executing a subset of the power-up sequence 有权
标题翻译：通过预测执行加电序列的子集来加速微处理器核心唤醒
公开(公告)号：US09298253B2
公开(公告)日：2016-03-29
申请号：US14026472
申请日：2013-09-13
申请人： International Business Machines Corporation
发明人： Pradip Bose , Alper Buyuktosunoglu , Hans Jacobson , Victor Zyuban
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/3287 , G06F1/26 , Y02D10/171 , Y02D50/20
摘要： A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any one of multiple circuits to a common voltage source, where a powered off circuit is disconnected from the common voltage source. A power-up sequencer includes an initial stages power-up component and a final stages power-up component. The final stages power-up component is configured to execute final stages of a power-up process for the powered off circuit, and the initial stages power-up component is configured to execute initial stages of the power-up process for the powered off circuit. The initial stages power-up component is activated in response to a predictive power-up request.
摘要翻译：为具有电源门控的集成电路提供了一种机制。电源接头开关被配置为将多个电路中的任何一个连接到一个公共电压源，其中断电电路与公共电压源断开。上电序列器包括初始阶段上电组件和最后阶段上电组件。最后阶段上电组件被配置为执行关闭电路的上电过程的最后阶段，并且初始阶段上电组件被配置为执行关断电路的上电过程的初始阶段。响应于预测的上电请求，初始级上电组件被激活。

8. 发明申请

US20150177796A1 ROTATING VOLTAGE CONTROL 有权
标题翻译：旋转电压控制
公开(公告)号：US20150177796A1
公开(公告)日：2015-06-25
申请号：US14134428
申请日：2013-12-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Pradip Bose , Alper Buyuktosunoglu , Hans M. Jacobson , Victor Zyuban
IPC分类号： G06F1/26
CPC分类号： G06F1/26 , G06F1/3296 , Y02D10/172
摘要： According to one embodiment, a system is provided that includes at least one power gated component and two or more power switch transistors configured to provide one or more conductive paths between a common power supply rail, the at least one power gated component, and a ground. The two or more power switch transistors each include a source terminal, a drain terminal, and a gate terminal configured to control current flow between the source and drain terminals. The system also includes a rotating voltage control coupled to the gate terminals and configured to apply a sequence of control signals rotating between an on-state and an off-state to each of the gate terminals while the at least one power gated component is turned on. A switch activation ratio level is programmable to set a number of power switch transistors in the on-state relative to a total number of power switch transistors.
摘要翻译：根据一个实施例，提供了一种系统，其包括至少一个电力选通部件和两个或更多个功率开关晶体管，其被配置为在公共供电轨道，至少一个电力门控部件和地面之间提供一个或多个导电路径。两个或更多个功率开关晶体管每个包括源极端子，漏极端子和被配置为控制源极和漏极端子之间的电流的栅极端子。该系统还包括耦合到栅极端子的旋转电压控制，并且被配置为在至少一个电力门控部件被接通的同时，将在导通状态和截止状态之间旋转的一系列控制信号施加到每个栅极端子。开关激活比电平是可编程的，以将多个功率开关晶体管相对于功率开关晶体管的总数设置为导通状态。

9. 发明授权

US09778726B2 Deterministic current based frequency optimization of processor chip 有权
公开(公告)号：US09778726B2
公开(公告)日：2017-10-03
申请号：US14833324
申请日：2015-08-24
申请人： International Business Machines Corporation
发明人： Malcolm S. Allen-Ware , Michael S. Floyd , Joshua D. Friedrich , Charles R. Lefurgy , Kirk D. Peterson , Karthick Rajamani , Srinivasan Ramani , Todd J. Rosedahl , Gregory S. Still , Brian W. Thompto , Victor Zyuban
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3206 , G06F1/3243 , Y02D10/126 , Y02D10/152
摘要： A method for adjusting a frequency of a processor is disclosed herein. In one embodiment, the method includes determining a total current and a temperature of the multi-core processor and estimating a leakage current for the multi-core processor. The method also includes calculating a switching current by subtracting the leakage current from the total current. The method also includes calculating an effective switching capacitance based at least in part on the switching current. The method also includes calculating a workload activity factor by dividing the effective switching capacitance by a predetermined effective switching capacitance stored in vital product data, and enforcing a turbo frequency limit of the multi-core processor based on the workload activity factor.

10. 发明申请

US20150082070A1 ACCELERATING THE MICROPROCESSOR CORE WAKEUP BY PREDICTIVELY EXECUTING A SUBSET OF THE POWER-UP SEQUENCE 有权
公开(公告)号：US20150082070A1
公开(公告)日：2015-03-19
申请号：US14026472
申请日：2013-09-13
申请人： International Business Machines Corporation
发明人： Pradip Bose , Alper Buyuktosunoglu , Hans Jacobson , Victor Zyuban
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/26 , Y02D10/171 , Y02D50/20
摘要： A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any one of multiple circuits to a common voltage source, where a powered off circuit is disconnected from the common voltage source. A power-up sequencer includes an initial stages power-up component and a final stages power-up component. The final stages power-up component is configured to execute final stages of a power-up process for the powered off circuit, and the initial stages power-up component is configured to execute initial stages of the power-up process for the powered off circuit. The initial stages power-up component is activated in response to a predictive power-up request.

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