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1. 发明授权

US09443050B2 Low-voltage swing circuit modifications 有权
标题翻译：低电压摆幅电路修改
公开(公告)号：US09443050B2
公开(公告)日：2016-09-13
申请号：US13956140
申请日：2013-07-31
申请人： Jacob Postman , Patrick Yin Chiang
发明人： Jacob Postman , Patrick Yin Chiang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5009 , G06F17/5045 , G06F17/5077 , G06F17/5081 , G06F2217/12
摘要： Electronic design automation (EDA) technologies are disclosed that analyze a circuit design for candidate low-voltage swing (LVS) modifications, report the impact of the candidate LVS modifications on circuit characteristics (such as area, timing and energy) and implement selected LVS modifications based on their impact on the circuit characteristics. Candidate LVS modifications comprise replacing existing standard low-voltage swing drivers and receivers, or inserting low-voltage swing drivers and receivers.
摘要翻译：公开了电子设计自动化（EDA）技术，分析候选低电压摆幅（LVS）修改的电路设计，报告候选LVS修改对电路特性（如面积，时序和能量）的影响，并实施所选的LVS修改基于它们对电路特性的影响。候选的LVS修改包括更换现有的标准低压摆动驱动器和接收器，或插入低电压摆动驱动器和接收器。

2. 发明申请

US20140040843A1 LOW-VOLTAGE SWING CIRCUIT MODIFICATIONS 有权
标题翻译：低电压振荡电路修改
公开(公告)号：US20140040843A1
公开(公告)日：2014-02-06
申请号：US13956140
申请日：2013-07-31
申请人： Jacob Postman , Patrick Yin Chiang
发明人： Jacob Postman , Patrick Yin Chiang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5009 , G06F17/5045 , G06F17/5077 , G06F17/5081 , G06F2217/12
摘要： Electronic design automation (EDA) technologies are disclosed that analyze a circuit design for candidate low-voltage swing (LVS) modifications, report the impact of the candidate LVS modifications on circuit characteristics (such as area, timing and energy) and implement selected LVS modifications based on their impact on the circuit characteristics. Candidate LVS modifications comprise replacing existing standard low-voltage swing drivers and receivers, or inserting low-voltage swing drivers and receivers.
摘要翻译：公开了电子设计自动化（EDA）技术，分析候选低电压摆幅（LVS）修改的电路设计，报告候选LVS修改对电路特性（如面积，时序和能量）的影响，并实施所选的LVS修改基于它们对电路特性的影响。候选的LVS修改包括更换现有的标准低压摆动驱动器和接收器，或插入低电压摆动驱动器和接收器。

3. 发明授权

US08487795B1 Time-interleaved track-and-hold circuit using distributed global sine-wave clock 失效
标题翻译：使用分布式全局正弦波时钟的时间交错跟踪和保持电路
公开(公告)号：US08487795B1
公开(公告)日：2013-07-16
申请号：US13450204
申请日：2012-04-18
申请人： Tao Jiang , Patrick Yin Chiang , Freeman Y. Zhong
发明人： Tao Jiang , Patrick Yin Chiang , Freeman Y. Zhong
IPC分类号： H03M1/00
CPC分类号： H03M1/0624 , G11C27/024 , H03M1/0836 , H03M1/1215
摘要： A time-interleaved track-and-hold circuit includes a clock generator adapted to receive a global sine-wave clock signal and to generate therefrom multiple square-wave output clock signals of different phases. The track-and-hold circuit includes a switching array operative in at least a track mode or a hold mode. The switching array includes multiple switch circuits, each switch circuit adapted to receive an analog input signal, a corresponding one of the output clock signals, and the global sine-wave clock signal. Each switch circuit is operative to utilize the corresponding one of the output clock signals during the track mode for tracking the analog input signal, and is operative during the hold mode to store the input signal sampled during the track mode as an output of the switch circuit and to utilize the global sine-wave clock signal during the hold mode for synchronizing sampling instants of the respective outputs of the switch circuits.
摘要翻译：时间交织的跟踪和保持电路包括适于接收全局正弦波时钟信号并由其产生不同相位的多个方波输出时钟信号的时钟发生器。跟踪和保持电路包括至少以轨道模式或保持模式工作的开关阵列。开关阵列包括多个开关电路，每个开关电路适于接收模拟输入信号，相应的一个输出时钟信号和全局正弦波时钟信号。每个开关电路可操作以在跟踪模式期间利用相应的一个输出时钟信号来跟踪模拟输入信号，并且在保持模式期间操作以将在跟踪模式期间采样的输入信号存储为开关电路的输出并且在保持模式期间利用全局正弦波时钟信号来同步开关电路的相应输出的采样时刻。

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