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1. 发明授权

US07152128B2 General input/output architecture, protocol and related methods to manage data integrity 有权
标题翻译：一般输入/输出架构，协议和相关方法来管理数据完整性
公开(公告)号：US07152128B2
公开(公告)日：2006-12-19
申请号：US10227600
申请日：2002-08-23
申请人： Eric R. Wehage , Jasmin Ajanovic , David Harriman , David M. Lee , Blaise Fanning , Buck Gremel , Ken Creta , Wayne Moore
发明人： Eric R. Wehage , Jasmin Ajanovic , David Harriman , David M. Lee , Blaise Fanning , Buck Gremel , Ken Creta , Wayne Moore
IPC分类号： G06F13/14
CPC分类号： H04L47/10 , G06F5/06 , G06F13/124 , G06F13/385 , G06F13/4059 , G06F13/42 , G06F13/4221 , G06F13/4252 , G06F13/4265 , G06F13/4269 , G06F13/4282 , H04L47/30
摘要： An enhanced general input/output communication architecture, protocol and related methods are presented. In one embodiment, a method is described comprising receiving a datagram at general input/output (GIO) interface from a remote GIO interface coupled through a GIO link, validating content of one or more packets embedded within the received datagram, and issuing an acknowledgment to the remote GIO interface that the datagram was successfully received on positive validation of the datagram before promoting the embedded packets to a transaction layer of the GIO interface. Other embodiments are also described.
摘要翻译：提出了一种增强的通用输入/输出通信架构，协议和相关方法。在一个实施例中，描述了一种方法，其包括从通过GIO链路耦合的远程GIO接口在一般输入/输出（GIO）接口处接收数据报，验证嵌入在所接收的数据报中的一个或多个分组的内容，以及向在将嵌入式数据包推送到GIO接口的事务层之前，数据报成功接收数据报的正确验证的远程GIO接口。还描述了其它实施例。

2. 发明申请

US20140185436A1 GENERAL INPUT/OUTPUT ARCHITECTURE, PROTOCOL AND RELATED METHODS TO IMPLEMENT FLOW CONTROL 审中-公开
标题翻译：一般输入/输出结构，协议和相关方法实施流量控制
公开(公告)号：US20140185436A1
公开(公告)日：2014-07-03
申请号：US14145384
申请日：2013-12-31
申请人： Jasmin Ajanovic , David Harriman , Blaise Fanning , David M. Lee
发明人： Jasmin Ajanovic , David Harriman , Blaise Fanning , David M. Lee
IPC分类号： H04L12/801
CPC分类号： H04L47/10 , G06F5/06 , G06F13/124 , G06F13/385 , G06F13/4059 , G06F13/42 , G06F13/4221 , G06F13/4252 , G06F13/4265 , G06F13/4269 , G06F13/4282 , H04L47/30
摘要： A storage device is provided to maintain a value of flow control credits allocated for a device on a channel and flow control logic is provided to receive a flow control signal over a link of an interconnect, the flow control signal indicating flow control credits allocated for the device on the channel. The flow control logic is further to update the value of flow control credits based on activity of the device on the channel.
摘要翻译：提供存储装置以维持为信道上的设备分配的流量控制信用的值，并且提供流控制逻辑以通过互连的链路接收流控制信号，所述流控制信号指示为设备在通道上。流量控制逻辑还基于通道上的设备的活动来更新流量控制信用的值。

3. 发明申请

US20140129747A1 GENERAL INPUT/OUTPUT ARCHITECTURE, PROTOCOL AND RELATED METHODS TO IMPLEMENT FLOW CONTROL 审中-公开
标题翻译：一般输入/输出结构，协议和相关方法实施流量控制
公开(公告)号：US20140129747A1
公开(公告)日：2014-05-08
申请号：US14145376
申请日：2013-12-31
申请人： Jasmin Ajanovic , David Harriman , Blaise Fanning , David M. Lee
发明人： Jasmin Ajanovic , David Harriman , Blaise Fanning , David M. Lee
IPC分类号： G06F13/42
CPC分类号： H04L47/10 , G06F5/06 , G06F13/124 , G06F13/385 , G06F13/4059 , G06F13/42 , G06F13/4221 , G06F13/4252 , G06F13/4265 , G06F13/4269 , G06F13/4282 , H04L47/30
摘要： A storage device is provided to maintain a count of flow control credits to be granted to a device in association with transactions over a channel to be implemented on a data link and control logic is provided to communicate, to the device, an indication of an amount of flow control credits for the device in association with a reset of the data link.
摘要翻译：提供一种存储装置，用于维持要通过要在数据链路上实现的信道上的事务相关联地授予设备的流量控制信用的计数，并且提供控制逻辑以向该设备传送数量的指示与数据链路的重置相关联的设备的流量控制信用。

4. 发明授权

US08566473B2 General input/output architecture, protocol and related methods to implement flow control 有权
标题翻译：一般输入/输出架构，协议和相关方法来实现流量控制
公开(公告)号：US08566473B2
公开(公告)日：2013-10-22
申请号：US12395497
申请日：2009-02-27
申请人： Jasmin Ajanovic , David Harriman , Blaise Fanning , David M. Lee
发明人： Jasmin Ajanovic , David Harriman , Blaise Fanning , David M. Lee
IPC分类号： G06F15/16
CPC分类号： H04L47/10 , G06F5/06 , G06F13/124 , G06F13/385 , G06F13/4059 , G06F13/42 , G06F13/4221 , G06F13/4252 , G06F13/4265 , G06F13/4269 , G06F13/4282 , H04L47/30
摘要： An enhanced general input/output communication architecture, protocol and related methods are presented. In one embodiment, a method for an enhanced general input/output communication architecture includes initializing a flow control mechanism within an general input/output (GIO) interface associated with a virtual channel upon initialization of the virtual channel, and tracking receive buffer availability in a remote GIO interface coupled with the GIO interface by the virtual channel by monitoring an indication associated with an amount of content transmitted from the GIO interface to the remote GIO interface.
摘要翻译：提出了一种增强的通用输入/输出通信架构，协议和相关方法。在一个实施例中，用于增强的一般输入/输出通信架构的方法包括：初始化虚拟通道初始化时初始化与虚拟通道相关联的通用输入/输出（GIO）接口内的流控制机制，以及在虚拟通道初始化时跟踪接收缓冲区可用性通过监视与从GIO接口发送到远程GIO接口的内容量相关联的指示，通过虚拟通道与远程GIO接口耦合到GIO接口。

5. 发明授权

US07536473B2 General input/output architecture, protocol and related methods to implement flow control 有权
标题翻译：一般输入/输出架构，协议和相关方法来实现流量控制
公开(公告)号：US07536473B2
公开(公告)日：2009-05-19
申请号：US10227601
申请日：2002-08-23
申请人： Jasmin Ajanovic , David Harriman , Blaise Fanning , David M. Lee
发明人： Jasmin Ajanovic , David Harriman , Blaise Fanning , David M. Lee
IPC分类号： G06F15/16
CPC分类号： H04L47/10 , G06F5/06 , G06F13/124 , G06F13/385 , G06F13/4059 , G06F13/42 , G06F13/4221 , G06F13/4252 , G06F13/4265 , G06F13/4269 , G06F13/4282 , H04L47/30
摘要： An enhanced general input/output communication architecture, protocol and related methods are presented.
摘要翻译：提出了一种增强的通用输入/输出通信架构，协议和相关方法。

6. 发明申请

US20090193164A1 General Input/Output Architecture, Protocol and Related Methods to Implement Flow Control 有权
标题翻译：一般输入/输出架构，协议和相关方法来实现流量控制
公开(公告)号：US20090193164A1
公开(公告)日：2009-07-30
申请号：US12395497
申请日：2009-02-27
申请人： Jasmin Ajanovic , David Harriman , Blaise Fanning , David M. Lee
发明人： Jasmin Ajanovic , David Harriman , Blaise Fanning , David M. Lee
IPC分类号： G06F13/14 , G06F13/00
CPC分类号： H04L47/10 , G06F5/06 , G06F13/124 , G06F13/385 , G06F13/4059 , G06F13/42 , G06F13/4221 , G06F13/4252 , G06F13/4265 , G06F13/4269 , G06F13/4282 , H04L47/30
摘要： An enhanced general input/output communication architecture, protocol and related methods are presented. In one embodiment, a method for an enhanced general input/output communication architecture includes initializing a flow control mechanism within an general input/output (GIO) interface associated with a virtual channel upon initialization of the virtual channel, and tracking receive buffer availability in a remote GIO interface coupled with the GIO interface by the virtual channel by monitoring an indication associated with an amount of content transmitted from the GIO interface to the remote GIO interface.
摘要翻译：提出了一种增强的通用输入/输出通信架构，协议和相关方法。在一个实施例中，用于增强的一般输入/输出通信架构的方法包括：初始化虚拟通道初始化时初始化与虚拟通道相关联的通用输入/输出（GIO）接口内的流控制机制，以及在虚拟通道初始化时跟踪接收缓冲区可用性通过监视与从GIO接口发送到远程GIO接口的内容量相关联的指示，通过虚拟通道与远程GIO接口耦合到GIO接口。

7. 发明授权

US07353313B2 General input/output architecture, protocol and related methods to manage data integrity 有权
标题翻译：一般输入/输出架构，协议和相关方法来管理数据完整性
公开(公告)号：US07353313B2
公开(公告)日：2008-04-01
申请号：US11585648
申请日：2006-10-23
申请人： Eric R. Wehage , Jasmin Ajanovic , David Harriman , David M. Lee , Blaise Fanning , Buck Gremel , Ken Creta , Wayne Moore
发明人： Eric R. Wehage , Jasmin Ajanovic , David Harriman , David M. Lee , Blaise Fanning , Buck Gremel , Ken Creta , Wayne Moore
IPC分类号： G06F13/14
CPC分类号： H04L47/10 , G06F5/06 , G06F13/124 , G06F13/385 , G06F13/4059 , G06F13/42 , G06F13/4221 , G06F13/4252 , G06F13/4265 , G06F13/4269 , G06F13/4282 , H04L47/30
摘要： An enhanced general input/output (EGIO) communication architecture, protocol and related methods are presented. The elements of an EGIO architecture may include one or more of a root complex (e.g., implemented within a bridge), a switch, and end-points, each incorporating at least a subset of EGIO features to support EGIO communication between such elements.
摘要翻译：提出了一种增强的一般输入/输出（EGIO）通信架构，协议和相关方法。 EGIO架构的元件可以包括根复合体（例如，在桥内实现），交换机和终点中的一个或多个，每个结合至少一个EGIO特征的子集以支持这些元素之间的EGIO通信。

8. 发明授权

US07184399B2 Method for handling completion packets with a non-successful completion status 有权
标题翻译：处理未完成状态的完成数据包的方法
公开(公告)号：US07184399B2
公开(公告)日：2007-02-27
申请号：US10040702
申请日：2001-12-28
申请人： David M. Lee , Kenneth C. Creta , Jasmin Ajanovic , Gary Solomon , David Harriman
发明人： David M. Lee , Kenneth C. Creta , Jasmin Ajanovic , Gary Solomon , David Harriman
IPC分类号： H04J1/16 , H04J3/14
CPC分类号： G06F13/4282 , G06F2213/0026
摘要： A requesting device and a completer device are coupled via a high-speed serial interface within a computer system. The requesting device transmits a packet for a request transaction to a completer device. The completer device checks for error conditions in the course of servicing the request. If an error condition is found then the completer device transmits a completion packet with a completion status of something other than successful. The completion packet includes a completer identification field. The requesting device records the completer identification value and indicates in a register that a completion packet has been received with a non-successful completion status.
摘要翻译：请求设备和完成设备经由计算机系统内的高速串行接口耦合。请求设备向完成设备发送用于请求事务的分组。完成设备在维护请求的过程中检查错误状况。如果发现错误条件，则完成装置发送完成状态为成功以外的完成数据包。完成分组包括完整的识别字段。请求设备记录完成的识别值，并在寄存器中指示已经接收到完成分组具有不成功的完成状态。

9. 发明授权

US09573252B1 Multiple size nut driver 有权
标题翻译：多尺寸螺母驱动
公开(公告)号：US09573252B1
公开(公告)日：2017-02-21
申请号：US14275411
申请日：2014-05-12
申请人： David M. Lee , Uttaran Hazarika
发明人： David M. Lee , Uttaran Hazarika
IPC分类号： B25B13/00 , B25B13/10 , B25B13/06
CPC分类号： B25B13/102 , B25B13/06
摘要： A nut driver for driving a nut within a range of nut sizes includes a housing. An open driver end thereof assumes a largest size of the nut sizes, and a selector end thereof terminates in a rotational knob that is positionable at any of a number of selectable radial positions. A cam is rotationally fixed with the knob and within the housing and terminates at a forward end with a selector ramp. A plurality of plungers are each slidably fixed within the housing and at a rear end thereof engage the selector ramp. Each plunger terminates at a forward end at a notched socket selector. A plurality of nested sockets each assume one of the different nut sizes and are slidably movable by at least one of the elongated plungers between a forward position within the open driver end of the housing and a rearward position.
摘要翻译：用于在螺母尺寸范围内驱动螺母的螺母驱动器包括壳体。其敞开的驱动器端部具有螺母尺寸的最大尺寸，并且其选择器端部终止于能够在多个可选径向位置中的任一个处定位的旋钮。凸轮通过旋钮旋转固定并且在壳体内，并且在前端具有选择器斜坡终止。多个柱塞各自可滑动地固定在壳体内，并且其后端接合选择器斜坡。每个柱塞在前端处于缺口插座选择器处。多个嵌套插座各自承担不同的螺母尺寸中的一个，并且通过至少一个细长的柱塞可滑动地移动，位于壳体的开放驱动器端部之间的向前位置和后部位置之间。

10. 发明授权

US08914556B2 Direct I/O access for system co-processors 有权
标题翻译：用于系统协处理器的直接I / O访问
公开(公告)号：US08914556B2
公开(公告)日：2014-12-16
申请号：US13997601
申请日：2011-09-30
申请人： William R. Magro , Robert J. Woodruff , David M. Lee , Arlin R. Davis , Mark Sean Hefty , Jerrie L. Coffman
发明人： William R. Magro , Robert J. Woodruff , David M. Lee , Arlin R. Davis , Mark Sean Hefty , Jerrie L. Coffman
IPC分类号： G06F13/28 , G06F13/14 , G06F13/16
CPC分类号： G06F13/16 , G06F13/14 , G06F13/28
摘要： Embodiments of the invention describe systems, apparatuses and methods that enable sharing Remote Direct Memory Access (RDMA) device hardware between a host and a peripheral device including a CPU and memory complex (alternatively referred to herein as a processor add-in card). Embodiments of the invention utilize interconnect hardware such as Peripheral Component Interconnect express (PCIe) hardware for peer-to-peer data transfers between processor add-in cards and RDMA devices. A host system may include modules or logic to map memory and registers to and/or from the RDMA device, thereby enabling I/O to be performed directly to and from user-mode applications on the processor add-in card, concurrently with host system I/O operations.
摘要翻译：本发明的实施例描述了能够在主机和包括CPU和存储器复合体（在本文中称为处理器附加卡）的外围设备之间共享远程直接存储器访问（RDMA）设备硬件的系统，装置和方法。本发明的实施例利用互连硬件，例如用于处理器附加卡和RDMA设备之间的对等数据传输的外围组件互连快速（PCIe）硬件。主机系统可以包括将存储器映射到RDMA设备和/或来自RDMA设备的寄存器的模块或逻辑，从而使I / O能够直接从处理器附加卡上的用户模式应用执行，与主机系统 I / O操作。

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