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    • 1. 发明授权
    • Thin film transistor array panel
    • 薄膜晶体管阵列面板
    • US07276732B2
    • 2007-10-02
    • US11234470
    • 2005-09-23
    • Je Hun LeeYang Ho BaeBeom Seok ChoChang Oh Jeong
    • Je Hun LeeYang Ho BaeBeom Seok ChoChang Oh Jeong
    • H01L29/04
    • H01L29/458G02F1/1368H01L27/12H01L27/124H01L27/1288
    • A thin film transistor array panel includes a source electrode and a drain electrode composed of a Mo alloy layer and a Cu layer, and an alloying element of the Mo alloy layer forms a nitride layer as a diffusion barrier against the Cu layer. The nitride layer can be formed between the Mo alloy layer and the Cu layer, between the Mo alloy layer and the semiconductor layer or in the Mo alloy layer. A method of fabricating a thin film transistor array panel includes forming a data line having a first conductive layer and a second conductive layer, the first conductive layer containing a Mo alloy and the second conductive layer containing Cu, and performing a nitrogen treatment so that an alloying element in the first conductive layer forms a nitride layer. The nitrogen treatment can be performed before forming the first conductive layer, after forming the first conductive layer, or during forming the first conductive layer.
    • 薄膜晶体管阵列面板包括由Mo合金层和Cu层构成的源电极和漏电极,Mo合金层的合金元素形成氮化物层作为对Cu层的扩散阻挡层。 可以在Mo合金层和Cu层之间,Mo合金层和半导体层之间或Mo合金层中形成氮化物层。 制造薄膜晶体管阵列面板的方法包括:形成具有第一导电层和第二导电层的数据线,所述第一导电层含有Mo合金,所述第二导电层含有Cu,并进行氮处理,使得 第一导电层中的合金元素形成氮化物层。 在形成第一导电层之前,在形成第一导电层之后,或者在形成第一导电层期间,可以进行氮处理。
    • 2. 发明授权
    • Method of fabricating a thin film transistor array panel
    • 制造薄膜晶体管阵列面板的方法
    • US07524706B2
    • 2009-04-28
    • US11844597
    • 2007-08-24
    • Je Hun LeeYang Ho BaeBeom Seok ChoChang Oh Jeong
    • Je Hun LeeYang Ho BaeBeom Seok ChoChang Oh Jeong
    • H01L21/00
    • H01L29/458G02F1/1368H01L27/12H01L27/124H01L27/1288
    • A thin film transistor array panel includes a source electrode and a drain electrode composed of a Mo alloy layer and a Cu layer, and an alloying element of the Mo alloy layer forms a nitride layer as a diffusion barrier against the Cu layer. The nitride layer can be formed between the Mo alloy layer and the Cu layer, between the Mo alloy layer and the semiconductor layer or in the Mo alloy layer. A method of fabricating a thin film transistor array panel includes forming a data line having a first conductive layer and a second conductive layer, the first conductive layer containing a Mo alloy and the second conductive layer containing Cu, and performing a nitrogen treatment so that an alloying element in the first conductive layer forms a nitride layer. The nitrogen treatment can be performed before forming the first conductive layer, after forming the first conductive layer, or during forming the first conductive layer.
    • 薄膜晶体管阵列面板包括由Mo合金层和Cu层构成的源电极和漏电极,Mo合金层的合金元素形成氮化物层作为对Cu层的扩散阻挡层。 可以在Mo合金层和Cu层之间,Mo合金层和半导体层之间或Mo合金层中形成氮化物层。 制造薄膜晶体管阵列面板的方法包括:形成具有第一导电层和第二导电层的数据线,所述第一导电层含有Mo合金,所述第二导电层含有Cu,并进行氮处理,使得 第一导电层中的合金元素形成氮化物层。 在形成第一导电层之前,在形成第一导电层之后,或者在形成第一导电层期间,可以进行氮处理。
    • 4. 发明授权
    • Thin film transistor having plural semiconductive oxides, thin film transistor array panel and display device including the same, and manufacturing method of thin film transistor
    • 具有多个半导体氧化物的薄膜晶体管,薄膜晶体管阵列面板及包括该半导体氧化物的显示装置以及薄膜晶体管的制造方法
    • US08686426B2
    • 2014-04-01
    • US13555889
    • 2012-07-23
    • Byung Du AhnJi Hun LimGun Hee KimKyoung Won LeeJe Hun Lee
    • Byung Du AhnJi Hun LimGun Hee KimKyoung Won LeeJe Hun Lee
    • H01L27/14
    • H01L29/7869H01L29/78696
    • A plural semiconductive oxides TFT (sos-TFT) provides improved electrical functionality in terms of charge-carrier mobility and/or threshold voltage variability. The sos-TFT may be used to form a thin film transistor array panel for display devices. An example sos-TFT includes: an insulated gate electrode; a first semiconductive oxide layer having a composition including a first semiconductive oxide; and a second semiconductive oxide layer having a different composition that also includes a semiconductive oxide. The first and second semiconductive oxide layers have respective channel regions that are capacitively influenced by a control voltage applied to the gate electrode. In one embodiment, the second semiconductive oxide layer includes at least one additional element that is not included in the first semiconductive oxide layer where the additional element is one of gallium (Ga), silicon (Si), niobium (Nb), hafnium (Hf), and germanium (Ge).
    • 多个半导体氧化物TFT(sos-TFT)在电荷载流子迁移率和/或阈值电压变化性方面提供改进的电功能。 sos-TFT可以用于形成用于显示装置的薄膜晶体管阵列面板。 示例sos-TFT包括:绝缘栅电极; 具有包含第一半导体氧化物的组成的第一半导体氧化物层; 以及具有不同组成的第二半导体氧化物层,其还包括半导体氧化物。 第一和第二半导体氧化物层具有由施加到栅电极的控制电压的电容性影响的各个沟道区。 在一个实施例中,第二半导体氧化物层包括至少一个附加元件,其不包括在第一半导体氧化物层中,其中附加元素是镓(Ga),硅(Si),铌(Nb),铪(Hf )和锗(Ge)。
    • 9. 发明授权
    • Thin-film transistor structure, as well as thin-film transistor and display device each having said structure
    • 薄膜晶体管结构,以及各自具有所述结构的薄膜晶体管和显示装置
    • US09093542B2
    • 2015-07-28
    • US14113322
    • 2012-04-19
    • Takeaki MaedaToshihiro KugimiyaJun Ho SongJe Hun LeeByung Du AhnGun Hee Kim
    • Takeaki MaedaToshihiro KugimiyaJun Ho SongJe Hun LeeByung Du AhnGun Hee Kim
    • H01L29/10H01L29/786G02F1/1368H01L27/12
    • H01L29/7869G02F1/1368H01L27/1222H01L29/78693
    • There is provided an oxide semiconductor layer capable of making stable the electric characteristics of a thin-film transistor without requiring an oxidatively-treated layer when depositing a passivation layer or the like in display devices such as organic EL displays and liquid crystal displays. The thin-film transistor structure of the present invention at least having, on a substrate, an oxide semiconductor layer, a source-drain electrode, and a passivation layer in order from the substrate side, wherein the oxide semiconductor layer is a stacked product of a first oxide semiconductor layer and a second oxide semiconductor layer; the first oxide semiconductor layer has a Zn content of 50 atomic % or more as a percentage of all metal elements contained therein, and the first oxide semiconductor layer is formed on the source-drain electrode and passivation layer side; the second oxide semiconductor layer contains Sn and at least one element selected from the group consisting of In, Ga, and Zn, and the second oxide semiconductor layer is formed on the substrate side; and the first oxide semiconductor layer is in direct contact both with the source-drain electrode and with the passivation layer.
    • 提供了一种氧化物半导体层,当在有机EL显示器和液晶显示器等显示装置中沉积钝化层等时,能够使薄膜晶体管的电特性稳定,而不需要氧化处理层。 本发明的薄膜晶体管结构至少在衬底上具有氧化物半导体层,源 - 漏电极和钝化层,从衬底侧开始,其中氧化物半导体层是 第一氧化物半导体层和第二氧化物半导体层; 第一氧化物半导体层的Zn含量占所有金属元素的百分比为50原子%以上,第一氧化物半导体层形成在源 - 漏电极和钝化层侧; 所述第二氧化物半导体层含有Sn和选自In,Ga和Zn中的至少一种元素,并且所述第二氧化物半导体层形成在所述基板侧; 并且第一氧化物半导体层与源 - 漏电极和钝化层直接接触。