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1. 发明授权

US08492190B2 Method for manufacturing display panel 失效
标题翻译：显示面板制造方法
公开(公告)号：US08492190B2
公开(公告)日：2013-07-23
申请号：US13472716
申请日：2012-05-16
申请人： Joo-Ae Youn , Yang-Ho Bae , Chang-Oh Jeong , Chong-Chul Chai , Pil-Sang Yun , Honglong Ning , Byeong-Beom Kim
发明人： Joo-Ae Youn , Yang-Ho Bae , Chang-Oh Jeong , Chong-Chul Chai , Pil-Sang Yun , Honglong Ning , Byeong-Beom Kim
IPC分类号： H01L29/04
CPC分类号： H01L33/0041 , H01L27/124 , H01L29/458
摘要： A method for manufacturing a display panel includes; formation of a lower gate line, disposal of a semiconductor on the lower gate line, disposal of a lower data line substantially perpendicular to the lower gate line, disposal of an insulating layer having a plurality of trenches exposing the lower gate line and the lower data line on the lower data line, disposal of an upper gate line directly on the lower gate line and within the plurality of trenches, and disposal of an upper data line directly on the lower data line and within the plurality of trenches.
摘要翻译：一种显示面板的制造方法，形成下栅极线，在下栅极线上处理半导体，处理基本上垂直于下栅极线的下数据线，处理具有暴露下栅极线的多个沟槽的绝缘层和较低数据在下数据线上行，直接在下栅极线上和多个沟槽内处理上栅极线，以及直接在下数据线上和多个沟槽内处置上数据线。

2. 发明申请

US20120135555A1 METHOD FOR MANUFACTURING THIN FILM TRANSISTOR ARRAY PANEL 有权
标题翻译：制造薄膜晶体管阵列的方法
公开(公告)号：US20120135555A1
公开(公告)日：2012-05-31
申请号：US13157806
申请日：2011-06-10
申请人： Jong-Hyun CHOUNG , Yang Ho BAE , Jean Ho SONG , O. Sung SEO , Sun-Young HONG , Hwa Yeul OH , Bong-Kyun KIM , Nam Seok SUH , Dong-Ju YANG , Wang Woo LEE
发明人： Jong-Hyun CHOUNG , Yang Ho BAE , Jean Ho SONG , O. Sung SEO , Sun-Young HONG , Hwa Yeul OH , Bong-Kyun KIM , Nam Seok SUH , Dong-Ju YANG , Wang Woo LEE
IPC分类号： H01L33/62
CPC分类号： H01L21/32134 , G02F1/136227 , H01L27/1288 , H01L29/41733
摘要： A method for manufacturing a thin film transistor array panel, including: sequentially forming a first silicon layer, a second silicon layer, a lower metal layer, and an upper metal layer on a gate insulating layer and a gate line; forming a first film pattern on the upper metal layer; forming a first lower metal pattern and a first upper metal pattern that includes a protrusion, by etching the upper metal layer and the lower metal layer; forming first and second silicon patterns by etching the first and second silicon layers; forming a second film pattern by ashing the first film pattern; forming a second upper metal pattern by etching the first upper metal pattern; forming a data line and a thin film transistor by etching the first lower metal pattern and the first and second silicon patterns; and forming a passivation layer and a pixel electrode on the resultant.
摘要翻译：一种制造薄膜晶体管阵列面板的方法，包括：在栅绝缘层和栅极线上依次形成第一硅层，第二硅层，下金属层和上金属层; 在上金属层上形成第一膜图案; 通过蚀刻上金属层和下金属层，形成第一下金属图案和包括突起的第一上金属图案; 通过蚀刻第一和第二硅层形成第一和第二硅图案; 通过灰化第一膜图案形成第二膜图案; 通过蚀刻第一上金属图案形成第二上金属图案; 通过蚀刻第一下金属图案和第一和第二硅图案来形成数据线和薄膜晶体管; 并在所得物上形成钝化层和像素电极。

3. 发明授权

US08158499B2 Wire structure, method for fabricating wire, thin film transistor substrate, and method for fabricating thin film transistor substrate 有权
标题翻译：线结构，制造线的方法，薄膜晶体管衬底以及制造薄膜晶体管衬底的方法
公开(公告)号：US08158499B2
公开(公告)日：2012-04-17
申请号：US12942910
申请日：2010-11-09
申请人： Je-hun Lee , Chang-oh Jeong , Beom-seok Cho , Yang-ho Bae
发明人： Je-hun Lee , Chang-oh Jeong , Beom-seok Cho , Yang-ho Bae
IPC分类号： H01L21/20
CPC分类号： H01L27/124 , G02F2001/13629 , G02F2001/136295 , H01L23/53238 , H01L27/12 , H01L29/41733 , H01L29/458 , H01L29/4908 , H01L2924/0002 , H01L2924/12044 , H01L2924/3011 , Y10T29/49117 , H01L2924/00
摘要： Provided are a wire structure, a method for fabricating a wire, a thin film transistor (TFT) substrate, and a method for fabricating a TFT substrate. The wire structure includes a barrier layer formed on a substrate and including copper nitride and a copper conductive layer formed on the barrier layer and including copper or a copper alloy
摘要翻译：提供一种线结构，制造线的方法，薄膜晶体管（TFT）基板以及制造TFT基板的方法。导线结构包括形成在基板上的阻挡层，其包含形成在阻挡层上的包含铜或铜合金的二氧化铜和铜导电层

4. 发明申请

US20110097961A1 DISPLAY PANEL AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：显示面板及其制造方法
公开(公告)号：US20110097961A1
公开(公告)日：2011-04-28
申请号：US12981287
申请日：2010-12-29
申请人： Min-Seok OH , Yang-Ho BAE , Pil-Sang YUN , Byeong-Beom KIM , Seung-Ha CHOI , Sang-Gab KIM , Chang-Ho JEONG , Shin-Il CHOI , Hong-Kee CHIN , Yu-Gwang JEONG , Dong-Ju YANG
发明人： Min-Seok OH , Yang-Ho BAE , Pil-Sang YUN , Byeong-Beom KIM , Seung-Ha CHOI , Sang-Gab KIM , Chang-Ho JEONG , Shin-Il CHOI , Hong-Kee CHIN , Yu-Gwang JEONG , Dong-Ju YANG
IPC分类号： H01J9/20
CPC分类号： H01L27/12 , G02F2001/136295 , H01L27/124 , H01L29/458
摘要： In a display panel and a method of manufacturing the display panel, a gate line, a data line, and source and drain electrodes including a same material as the data line are formed on a substrate constituting the display panel, and the data line includes an aluminum based alloy containing sufficient nickel to inhibit corrosion during dry etching. The corrosion resistance of the AlNi-containing alloy helps prevent corrosion of the data line, the source electrode, and the drain electrode during selective dry etching that shapes these lines and electrodes.
摘要翻译：在显示面板和制造显示面板的方法中，在构成显示面板的基板上形成包括与数据线相同材料的栅极线，数据线以及源极和漏极，并且数据线包括铝基合金含有足够的镍以在干蚀刻期间抑制腐蚀。含有AlNi的合金的耐腐蚀性有助于防止在形成这些线和电极的选择性干蚀刻期间数据线，源电极和漏电极的腐蚀。

5. 发明授权

US07879662B2 Thin film transistor, thin film transistor substrate including the same and method of manufacturing the same 有权
标题翻译：薄膜晶体管，包括其的薄膜晶体管基板及其制造方法
公开(公告)号：US07879662B2
公开(公告)日：2011-02-01
申请号：US12573385
申请日：2009-10-05
申请人： Yang-Ho Bae , Chang-Oh Jeong , Byeong-Beom Kim
发明人： Yang-Ho Bae , Chang-Oh Jeong , Byeong-Beom Kim
IPC分类号： H01L21/00
CPC分类号： H01L29/458 , H01L27/124
摘要： A thin film transistor showing desirable contact characteristics during contact with indium tin oxide (ITO) or indium zinc oxide (IZO), in which a first conductive pattern including a gate electrode and a second conductive pattern including a source electrode and a drain electrode are formed without an etching process, a TFT substrate including the TFTs, and a method of manufacturing the same. The thin film transistor includes a gate electrode formed of a first conductive layer, a gate insulating layer covering the gate electrode, a semiconductor layer forming a channel on the gate insulating layer; an ohmic contact layer formed on the semiconductor layer, and a source electrode and a drain electrode formed of a second conductive layer and of a third conductive layer. The second conductive layer includes an aluminum-nickel alloy and nitrogen and is formed on the semiconductor layer. The third conductive layer includes an aluminum-nickel alloy and is formed on the second conductive layer.
摘要翻译：在与铟锡氧化物（ITO）或铟锌氧化物（IZO）接触期间显示出期望的接触特性的薄膜晶体管，其中形成包括栅电极的第一导电图案和包括源电极和漏电极的第二导电图案没有蚀刻处理，包括TFT的TFT基板及其制造方法。薄膜晶体管包括由第一导电层形成的栅电极，覆盖栅电极的栅极绝缘层，在栅极绝缘层上形成沟道的半导体层; 形成在半导体层上的欧姆接触层，以及由第二导电层和第三导电层形成的源电极和漏电极。第二导电层包括铝 - 镍合金和氮，并形成在半导体层上。第三导电层包括铝镍合金，并形成在第二导电层上。

6. 发明授权

US07759738B2 Array substrate and method of manufacturing the same 有权
标题翻译：阵列基板及其制造方法
公开(公告)号：US07759738B2
公开(公告)日：2010-07-20
申请号：US12269748
申请日：2008-11-12
申请人： Jang-Soo Kim , Hong-Long Ning , Bong-Kyun Kim , Hong-Sick Park , Shi-Yul Kim , Chang-Oh Jeong , Sang-Gab Kim , Jae-Hyoung Youn , Woo-Geun Lee , Yang-Ho Bae , Pil-Sang Yun , Jong-Hyun Choung , Sun-Young Hong , Ki-Won Kim , Byeong-Jin Lee , Young-Wook Lee , Jong-In Kim , Byeong-Beom Kim , Nam-Seok Suh
发明人： Jang-Soo Kim , Hong-Long Ning , Bong-Kyun Kim , Hong-Sick Park , Shi-Yul Kim , Chang-Oh Jeong , Sang-Gab Kim , Jae-Hyoung Youn , Woo-Geun Lee , Yang-Ho Bae , Pil-Sang Yun , Jong-Hyun Choung , Sun-Young Hong , Ki-Won Kim , Byeong-Jin Lee , Young-Wook Lee , Jong-In Kim , Byeong-Beom Kim , Nam-Seok Suh
IPC分类号： H01L29/04 , H01L29/10 , H01L29/15
CPC分类号： G02F1/13458 , G02F1/136286 , G02F2001/136295 , H01L27/1218 , H01L27/124 , H01L27/1288
摘要： A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed.
摘要翻译：栅极线包括形成在基底基板上的第一籽晶层和形成在第一籽晶层上的第一金属层。在基底基板上形成第一绝缘层。在基底基板上形成第二绝缘层。这里，在与栅极线交叉的方向上通过第二绝缘层形成线沟槽。数据线包括形成在线沟槽下方的第二晶种层和形成在线沟槽中的第二金属层。像素电极形成在基底基板的像素区域中。因此，使用绝缘层形成预定深度的沟槽，并且通过电镀方法形成金属层，从而可以形成具有足够厚度的金属线。

7. 发明申请

US20090117333A1 METHOD OF MANUFACTURING DISPLAY DEVICE AND DISPLAY DEVICE THEREFROM 审中-公开
标题翻译：制造显示装置的方法和显示装置
公开(公告)号：US20090117333A1
公开(公告)日：2009-05-07
申请号：US12198746
申请日：2008-08-26
申请人： Byeong-Jin Lee , Hong-sick Park , Hong-long Ning , Chang-oh Jeong , Yang-ho Bae , Pil-sang Yun , Sung-hen Cho , Ki-Yong Song , Seung-jae Jung , Byeong-beom Kim
发明人： Byeong-Jin Lee , Hong-sick Park , Hong-long Ning , Chang-oh Jeong , Yang-ho Bae , Pil-sang Yun , Sung-hen Cho , Ki-Yong Song , Seung-jae Jung , Byeong-beom Kim
IPC分类号： B32B3/02 , B05D5/12
CPC分类号： H01L21/0331 , C23C18/1608 , C23C18/165 , C23C18/1879 , C23C18/31 , G02F2001/136295 , H01L27/124 , H01L27/1288 , Y10T428/24479
摘要： A method of manufacturing a display device includes: forming an auxiliary layer including at least one of metal and a metal oxide on an insulating substrate; forming a photoresist layer pattern partially exposing the auxiliary layer on the auxiliary layer; forming a trench on the insulating substrate by etching the exposed auxiliary layer and the insulating substrate under the exposed auxiliary layer; forming a seed layer including a first seed layer disposed on the photoresist layer pattern and a second seed layer disposed in the trench; removing the photoresist layer pattern and the first seed layer by lifting off the photoresist layer pattern; removing the auxiliary layer remaining on the insulating substrate after lifting off the photoresist layer pattern; and forming a main wiring layer on the second seed layer by electroless plating.
摘要翻译：一种制造显示装置的方法包括：在绝缘基板上形成包括金属和金属氧化物中的至少一种的辅助层; 形成部分地使辅助层上的辅助层暴露的光致抗蚀剂层图案; 通过在暴露的辅助层下蚀刻暴露的辅助层和绝缘基板，在绝缘基板上形成沟槽; 形成种子层，其包括设置在所述光致抗蚀剂层图案上的第一种子层和设置在所述沟槽中的第二种子层; 通过剥离光致抗蚀剂层图案去除光致抗蚀剂层图案和第一种子层; 在剥离光致抗蚀剂层图案之后去除残留在绝缘基板上的辅助层; 以及通过无电解电镀在所述第二晶种层上形成主布线层。

8. 发明授权

US07524706B2 Method of fabricating a thin film transistor array panel 有权
标题翻译：制造薄膜晶体管阵列面板的方法
公开(公告)号：US07524706B2
公开(公告)日：2009-04-28
申请号：US11844597
申请日：2007-08-24
申请人： Je Hun Lee , Yang Ho Bae , Beom Seok Cho , Chang Oh Jeong
发明人： Je Hun Lee , Yang Ho Bae , Beom Seok Cho , Chang Oh Jeong
IPC分类号： H01L21/00
CPC分类号： H01L29/458 , G02F1/1368 , H01L27/12 , H01L27/124 , H01L27/1288
摘要： A thin film transistor array panel includes a source electrode and a drain electrode composed of a Mo alloy layer and a Cu layer, and an alloying element of the Mo alloy layer forms a nitride layer as a diffusion barrier against the Cu layer. The nitride layer can be formed between the Mo alloy layer and the Cu layer, between the Mo alloy layer and the semiconductor layer or in the Mo alloy layer. A method of fabricating a thin film transistor array panel includes forming a data line having a first conductive layer and a second conductive layer, the first conductive layer containing a Mo alloy and the second conductive layer containing Cu, and performing a nitrogen treatment so that an alloying element in the first conductive layer forms a nitride layer. The nitrogen treatment can be performed before forming the first conductive layer, after forming the first conductive layer, or during forming the first conductive layer.
摘要翻译：薄膜晶体管阵列面板包括由Mo合金层和Cu层构成的源电极和漏电极，Mo合金层的合金元素形成氮化物层作为对Cu层的扩散阻挡层。可以在Mo合金层和Cu层之间，Mo合金层和半导体层之间或Mo合金层中形成氮化物层。制造薄膜晶体管阵列面板的方法包括：形成具有第一导电层和第二导电层的数据线，所述第一导电层含有Mo合金，所述第二导电层含有Cu，并进行氮处理，使得第一导电层中的合金元素形成氮化物层。在形成第一导电层之前，在形成第一导电层之后，或者在形成第一导电层期间，可以进行氮处理。

9. 发明申请

US20080173870A1 THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF PRODUCING THE SAME 审中-公开
标题翻译：薄膜晶体管基板及其制造方法
公开(公告)号：US20080173870A1
公开(公告)日：2008-07-24
申请号：US11929586
申请日：2007-10-30
申请人： Byeong-beom Kim , Chang-oh Jeong , Yang-ho Bae
发明人： Byeong-beom Kim , Chang-oh Jeong , Yang-ho Bae
IPC分类号： H01L29/04 , H01L21/336
CPC分类号： H01L27/124 , G02F1/13439
摘要： A thin film transistor substrate having low resistivity and reduced contact resistance includes a gate wiring line formed on an insulating substrate, a data wiring line crossing the gate wiring line while being insulated from the gate wiring line, and a pixel electrode connected to a portion of the data wiring line and including a zinc oxide layer pattern doped with a dopant and an anti-oxidizing substance layer pattern.
摘要翻译：具有低电阻率和降低的接触电阻的薄膜晶体管基板包括形成在绝缘基板上的栅极布线，与栅极布线相交而与栅极布线绝缘的数据布线，以及连接到栅极布线的一部分的像素电极数据布线并且包括掺杂有掺杂剂的氧化锌层图案和抗氧化物质层图案。

10. 发明申请

US20080138942A1 THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：薄膜晶体管阵列及其制造方法
公开(公告)号：US20080138942A1
公开(公告)日：2008-06-12
申请号：US12031121
申请日：2008-02-14
申请人： Je-Hun LEE , Yang-Ho BAE , Beom-Seok CHO , Chang-Oh JEONG
发明人： Je-Hun LEE , Yang-Ho BAE , Beom-Seok CHO , Chang-Oh JEONG
IPC分类号： H01L21/336
CPC分类号： H01L27/3279 , H01L27/124 , H01L27/1288 , H01L51/0023 , H01L51/56
摘要： The invention provides a thin film transistor (TFT) array panel that includes an insulating substrate; a gate line formed on the insulating substrate and having a first layer of an Al containing metal, a second layer of a Cu containing metal that is thicker than the first layer, and a gate electrode; a gate insulating layer arranged on the gate line; a semiconductor arranged on the gate insulating layer; a data line having a source electrode and arranged on the gate insulating layer and the semiconductor; a drain electrode arranged on the gate insulating layer and the semiconductor and facing the source electrode; a passivation layer having a contact hole and arranged on the data line and the drain electrode; and a pixel electrode arranged on the passivation layer and coupled with the drain electrode through the contact hole.
摘要翻译：本发明提供一种薄膜晶体管（TFT）阵列面板，其包括绝缘基板; 形成在所述绝缘基板上并具有含有Al的金属的第一层，比所述第一层更厚的含Cu金属的第二层的栅极线和栅电极; 栅极绝缘层，布置在栅极线上; 布置在栅绝缘层上的半导体; 数据线，其具有源电极并且布置在所述栅极绝缘层和所述半导体上; 布置在所述栅绝缘层和所述半导体上并面对所述源电极的漏电极; 钝化层，其具有接触孔并且布置在所述数据线和所述漏电极上; 以及设置在钝化层上并通过接触孔与漏电极耦合的像素电极。

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