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1. 发明授权

US08094503B2 Method of programming an array of NMOS EEPROM cells that minimizes bit disturbances and voltage withstand requirements for the memory array and supporting circuits 有权
标题翻译：编程阵列的NMOS EEPROM单元的方法，其最小化存储器阵列和支持电路的位干扰和耐压要求
公开(公告)号：US08094503B2
公开(公告)日：2012-01-10
申请号：US12854504
申请日：2010-08-11
申请人： Jeffrey A. Shields , Kent D. Hewitt , Donald S. Gerber
发明人： Jeffrey A. Shields , Kent D. Hewitt , Donald S. Gerber
IPC分类号： G11C16/04
CPC分类号： G11C16/0416 , G11C16/12 , G11C16/16 , G11C16/3427 , H01L27/0207 , H01L27/115 , H01L27/11803
摘要： A method for programming and erasing an array of NMOS electrically erasable programmable read only memory (EEPROM) cells that minimizes bit disturbances and high voltage requirements for the memory array cells and supporting circuits. In addition, the array of N-channel memory cells may be separated into independently programmable memory segments by creating multiple, electrically isolated P-wells upon which the memory segments are fabricated. The multiple, electrically isolated P-wells may be created, for example, by p-n junction isolation or dielectric isolation.
摘要翻译：一种用于编程和擦除NMOS电可擦除可编程只读存储器（EEPROM）单元的阵列的方法，其使存储器阵列单元和支持电路的位干扰和高电压要求最小化。此外，N沟道存储单元的阵列可以通过产生多个电隔离的P阱来分离成独立可编程的存储器段，在其上制造存储器段。多个电隔离的P阱可以例如通过p-n结隔离或电介质隔离来产生。

2. 发明授权

US07817474B2 Method for programming and erasing an array of NMOS EEPROM cells that minimizes bit disturbances and voltage withstand requirements for the memory array and supporting circuits 有权
标题翻译：用于编程和擦除NMOS EEPROM单元阵列的方法，可最大限度地减少存储器阵列和支持电路的位干扰和电压耐受要求
公开(公告)号：US07817474B2
公开(公告)日：2010-10-19
申请号：US12331542
申请日：2008-12-10
申请人： Jeffrey A. Shields , Kent D. Hewitt , Donald S. Gerber
发明人： Jeffrey A. Shields , Kent D. Hewitt , Donald S. Gerber
IPC分类号： G11C16/00
CPC分类号： G11C16/0416 , G11C16/12 , G11C16/16 , G11C16/3427 , H01L27/0207 , H01L27/115 , H01L27/11803
摘要： A method for programming and erasing an array of NMOS electrically erasable programmable read only memory (EEPROM) cells that minimizes bit disturbances and high voltage requirements for the memory array cells and supporting circuits. In addition, the array of N-channel memory cells may be separated into independently programmable memory segments by creating multiple, electrically isolated P-wells upon which the memory segments are fabricated. The multiple, electrically isolated P-wells may be created, for example, by p-n junction isolation or dielectric isolation.
摘要翻译：一种用于编程和擦除NMOS电可擦除可编程只读存储器（EEPROM）单元的阵列的方法，其最小化存储器阵列单元和支持电路的位干扰和高电压要求。此外，N沟道存储单元的阵列可以通过产生多个电隔离的P阱来分离成独立可编程的存储器段，在其上制造存储器段。多个电隔离的P阱可以例如通过p-n结隔离或电介质隔离来产生。

3. 发明申请

US20090122618A1 Method for Programming and Erasing an Array of NMOS EEPROM Cells that Minimizes Bit Disturbances and Voltage Withstand Requirements for the Memory Array and Supporting Circuits 有权
标题翻译：用于编程和擦除阵列的NMOS EEPROM单元的方法，可以最大限度地减少存储器阵列和支持电路的位干扰和耐压要求
公开(公告)号：US20090122618A1
公开(公告)日：2009-05-14
申请号：US12331542
申请日：2008-12-10
申请人： Jeffrey A. Shields , Kent D. Hewitt , Donald S. Gerber
发明人： Jeffrey A. Shields , Kent D. Hewitt , Donald S. Gerber
IPC分类号： G11C16/06
CPC分类号： G11C16/0416 , G11C16/12 , G11C16/16 , G11C16/3427 , H01L27/0207 , H01L27/115 , H01L27/11803
摘要： A method for programming and erasing an array of NMOS electrically erasable programmable read only memory (EEPROM) cells that minimizes bit disturbances and high voltage requirements for the memory array cells and supporting circuits. In addition, the array of N-channel memory cells may be separated into independently programmable memory segments by creating multiple, electrically isolated P-wells upon which the memory segments are fabricated. The multiple, electrically isolated P-wells may be created, for example, by p-n junction isolation or dielectric isolation.
摘要翻译：一种用于编程和擦除NMOS电可擦除可编程只读存储器（EEPROM）单元的阵列的方法，其最小化存储器阵列单元和支持电路的位干扰和高电压要求。此外，N沟道存储单元的阵列可以通过产生多个电隔离的P阱来分离成独立可编程的存储器段，在其上制造存储器段。多个电隔离的P阱可以例如通过p-n结隔离或电介质隔离来产生。

4. 发明申请

US20100302857A1 METHOD OF PROGRAMMING AN ARRAY OF NMOS EEPROM CELLS THAT MINIMIZES BIT DISTURBANCES AND VOLTAGE WITHSTAND REQUIREMENTS FOR THE MEMORY ARRAY AND SUPPORTING CIRCUITS 有权
标题翻译：对存储器阵列和支持电路最小化位元干扰和电压耐受要求的NMOS EEPROM电池阵列的编程方法
公开(公告)号：US20100302857A1
公开(公告)日：2010-12-02
申请号：US12854504
申请日：2010-08-11
申请人： Jeffrey A. Shields , Kent D. Hewitt , Donald S. Gerber
发明人： Jeffrey A. Shields , Kent D. Hewitt , Donald S. Gerber
IPC分类号： G11C16/04
CPC分类号： G11C16/0416 , G11C16/12 , G11C16/16 , G11C16/3427 , H01L27/0207 , H01L27/115 , H01L27/11803
摘要： A method for programming and erasing an array of NMOS electrically erasable programmable read only memory (EEPROM) cells that minimizes bit disturbances and high voltage requirements for the memory array cells and supporting circuits. In addition, the array of N-channel memory cells may be separated into independently programmable memory segments by creating multiple, electrically isolated P-wells upon which the memory segments are fabricated. The multiple, electrically isolated P-wells may be created, for example, by p-n junction isolation or dielectric isolation.
摘要翻译：一种用于编程和擦除NMOS电可擦除可编程只读存储器（EEPROM）单元的阵列的方法，其最小化存储器阵列单元和支持电路的位干扰和高电压要求。此外，N沟道存储单元的阵列可以通过产生多个电隔离的P阱来分离成独立可编程的存储器段，在其上制造存储器段。多个电隔离的P阱可以例如通过p-n结隔离或电介质隔离来产生。

5. 发明授权

US06504191B2 Independently programmable memory segments within a PMOS electrically erasable programmable read only memory array achieved by N-well separation and method therefor 有权
公开(公告)号：US06504191B2
公开(公告)日：2003-01-07
申请号：US09972563
申请日：2001-10-08
申请人： Donald S. Gerber , Randy L. Yach , Kent D. Hewitt , Gianpaolo Spadini
发明人： Donald S. Gerber , Randy L. Yach , Kent D. Hewitt , Gianpaolo Spadini
IPC分类号： H01L2980
CPC分类号： H01L27/11521 , G11C16/0416 , H01L27/0207 , H01L27/11519
摘要： An array of P-channel memory cells is separated into independently programmable memory segments by creating multiple, electrically isolated N-wells upon which the memory segments are fabricated. The methods for creating the multiple, electrically isolated N-wells include p-n junction isolation and dielectric isolation.

6. 发明授权

US06300183B1 Independently programmable memory segments within a PMOS electrically erasable programmable read only memory array achieved by N-well separation and method therefor 有权
标题翻译：通过N阱分离实现的PMOS电可擦除可编程只读存储器阵列中的独立可编程存储器段及其方法
公开(公告)号：US06300183B1
公开(公告)日：2001-10-09
申请号：US09272675
申请日：1999-03-19
申请人： Donald S. Gerber , Randy L. Yach , Kent D. Hewitt , Gianpaolo Spadini
发明人： Donald S. Gerber , Randy L. Yach , Kent D. Hewitt , Gianpaolo Spadini
IPC分类号： H01L218238
CPC分类号： H01L27/11521 , G11C16/0416 , H01L27/0207 , H01L27/11519
摘要： An array of P-channel memory cells is separated into independently programmable memory segments by creating multiple, electrically isolated N-wells upon which the memory segments are fabricated. The methods for creating the multiple, electrically isolated N-wells include p-n junction isolation and dielectric isolation.
摘要翻译：通过产生多个电隔离的N阱，将P阵列的P沟道存储单元分成独立的可编程存储器段，在其上制造存储器段。用于产生多个电隔离的N阱的方法包括p-n结隔离和介电隔离。

7. 发明授权

US06222761B1 Method for minimizing program disturb in a memory cell 有权
标题翻译：用于最小化存储器单元中的程序干扰的方法
公开(公告)号：US06222761B1
公开(公告)日：2001-04-24
申请号：US09617281
申请日：2000-07-17
申请人： Donald S. Gerber , Kent Hewitt , Jeffrey A. Shields
发明人： Donald S. Gerber , Kent Hewitt , Jeffrey A. Shields
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C16/16
摘要： A method of applying voltages to a memory cell, such as a P-channel EEPROM cell, and in particular to applying voltages to the cell during an erase operation of the cell is described. The method recognizes that during an erase, memory cells sharing deselected word lines are susceptible to a type of program disturb which is subtle and gradually causes corruption and loss of data over many programming cycles. The method of the present invention applies a voltage to deselected word lines, which is lower in magnitude than a programming voltage. This reduces the rate at which program disturb occurs, markedly increasing the number of programming cycles to which the deselected cells may be subjected before becoming susceptible to loss of data. The endurance of the memory array is thus significantly extended.
摘要翻译：描述了一种向诸如P沟道EEPROM单元的存储单元施加电压的方法，特别是在单元的擦除操作期间向单元施加电压的方法。该方法认识到，在擦除期间，共享取消选择的字线的存储器单元容易受到一种程序干扰的影响，该程序干扰是微妙的，并且在许多编程周期中逐渐导致数据损坏和丢失。本发明的方法将电压施加到低于编程电压的取消选择字线。这降低了编程干扰发生的速率，显着增加了在忽略数据丢失之前取消选择的单元可能经受的编程周期数。因此，存储器阵列的耐久性显着延长。

8. 发明授权

US06236595B1 Programming method for a memory cell 有权
标题翻译：存储单元的编程方法
公开(公告)号：US06236595B1
公开(公告)日：2001-05-22
申请号：US09617280
申请日：2000-07-17
申请人： Donald S. Gerber , Kent Hewitt , Jeffrey A. Shields , David M. Davies
发明人： Donald S. Gerber , Kent Hewitt , Jeffrey A. Shields , David M. Davies
IPC分类号： G11C1604
CPC分类号： G11C16/3427 , G11C16/0425 , G11C16/10 , G11C16/14 , G11C2216/28
摘要： A method of writing and selectively erasing bits in a selected group of memory cells that significantly reduces the likelihood of disturbing data stored in other, non-selected groups of memory cells is disclosed. The method varies the bias voltages applied to bit lines in unselected cells depending upon the selected or non-selected state of the cells. This reduces the voltage differential applied to the unselected cells, reducing the possibility of inadvertently causing unwanted changes in the amount of charge stored on the respective floating gates of the unselected cells. The method of the present invention improves electrical isolation between columns of cells without increasing the distance between the cells.
摘要翻译：公开了一种写入和选择性地擦除选定组的存储器单元中的位的方法，其显着地降低了存储在其它未选择的存储器单元组中的数据的干扰的可能性。该方法根据所选择的或未选择的单元状态改变施加到未选择单元中位线的偏置电压。这降低了施加到未选择的单元的电压差，减少了无意中引起存储在未选择单元的相应浮动栅极上的电荷量的不期望的变化的可能性。本发明的方法改善了电池柱之间的电隔离，而不增加电池之间的距离。

9. 发明授权

US5073230A Means and methods of lifting and relocating an epitaxial device layer 失效
标题翻译：提升和重新定位外延器件层的方法和方法
公开(公告)号：US5073230A
公开(公告)日：1991-12-17
申请号：US510276
申请日：1990-04-17
申请人： George N. Maracas , Ronald A. Ruechner , Donald S. Gerber
发明人： George N. Maracas , Ronald A. Ruechner , Donald S. Gerber
IPC分类号： H01L21/20
CPC分类号： H01L21/02546 , H01L21/6835 , H01L21/7813 , H01L2221/6835 , H01L2221/68368 , H01L2221/68381 , Y10S117/915
摘要： Means and methods for obtaining the separation of large area semiconductorpitaxial device layers from the substrates on which they are grown, the transfer of the grown epi layers to a new host substrate for mounted alignment with features of the new host, and reuse of the original substrate.
摘要翻译：用于获得大面积半导体外延器件层从其生长的衬底上分离的方法和方法，将生长的epi层转移到新的主体衬底以与新主体的特征进行安装对准，以及重新使用原始基质。

10. 发明授权

US06432773B1 Memory cell having an ONO film with an ONO sidewall and method of fabricating same 有权
标题翻译：具有具有ONO侧壁的ONO膜的存储单元及其制造方法
公开(公告)号：US06432773B1
公开(公告)日：2002-08-13
申请号：US09288597
申请日：1999-04-08
申请人： Donald S. Gerber , Neil Deutscher , Robert P. Ma
发明人： Donald S. Gerber , Neil Deutscher , Robert P. Ma
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/511
摘要： A merged two transistor memory cell of an EEPROM, and method of fabricating same, is provided. The memory cell includes a substrate and insulating layer formed on the substrate. It also includes a memory transistor having a floating gate and a control gate, and a select transistor having a gate that is shared with the memory transistor. The memory cell is configured so that the shared gate serves both as the control gate of the memory transistor and the wordline of the select transistor. The memory cell further includes an ONO stack film that is disposed between the floating gate and the shared gate. In fabricating the memory, the ONO stack film is formed adjacent to the top and side surfaces of the floating gate. The ONO stack film is also formed so as not to be interposed between a potion of the shared gate that is adjacent to the substrate and the insulating layer.
摘要翻译：提供EEPROM的合并二晶体管存储单元及其制造方法。存储单元包括在基板上形成的基板和绝缘层。它还包括具有浮置栅极和控制栅极的存储晶体管，以及具有与存储晶体管共享的栅极的选择晶体管。存储单元被配置为使得共享栅极同时用作存储晶体管的控制栅极和选择晶体管的字线。存储单元还包括设置在浮动栅极和共享栅极之间的ONO堆叠膜。在制造存储器时，ONO叠层膜与浮栅的顶表面和侧表面相邻地形成。 ONO叠层膜也形成为不被插入在与基板相邻的共享栅极的部分和绝缘层之间。

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