专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08094503B2 Method of programming an array of NMOS EEPROM cells that minimizes bit disturbances and voltage withstand requirements for the memory array and supporting circuits 有权
标题翻译：编程阵列的NMOS EEPROM单元的方法，其最小化存储器阵列和支持电路的位干扰和耐压要求
公开(公告)号：US08094503B2
公开(公告)日：2012-01-10
申请号：US12854504
申请日：2010-08-11
申请人： Jeffrey A. Shields , Kent D. Hewitt , Donald S. Gerber
发明人： Jeffrey A. Shields , Kent D. Hewitt , Donald S. Gerber
IPC分类号： G11C16/04
CPC分类号： G11C16/0416 , G11C16/12 , G11C16/16 , G11C16/3427 , H01L27/0207 , H01L27/115 , H01L27/11803
摘要： A method for programming and erasing an array of NMOS electrically erasable programmable read only memory (EEPROM) cells that minimizes bit disturbances and high voltage requirements for the memory array cells and supporting circuits. In addition, the array of N-channel memory cells may be separated into independently programmable memory segments by creating multiple, electrically isolated P-wells upon which the memory segments are fabricated. The multiple, electrically isolated P-wells may be created, for example, by p-n junction isolation or dielectric isolation.
摘要翻译：一种用于编程和擦除NMOS电可擦除可编程只读存储器（EEPROM）单元的阵列的方法，其使存储器阵列单元和支持电路的位干扰和高电压要求最小化。此外，N沟道存储单元的阵列可以通过产生多个电隔离的P阱来分离成独立可编程的存储器段，在其上制造存储器段。多个电隔离的P阱可以例如通过p-n结隔离或电介质隔离来产生。

2. 发明申请

US20100302857A1 METHOD OF PROGRAMMING AN ARRAY OF NMOS EEPROM CELLS THAT MINIMIZES BIT DISTURBANCES AND VOLTAGE WITHSTAND REQUIREMENTS FOR THE MEMORY ARRAY AND SUPPORTING CIRCUITS 有权
标题翻译：对存储器阵列和支持电路最小化位元干扰和电压耐受要求的NMOS EEPROM电池阵列的编程方法
公开(公告)号：US20100302857A1
公开(公告)日：2010-12-02
申请号：US12854504
申请日：2010-08-11
申请人： Jeffrey A. Shields , Kent D. Hewitt , Donald S. Gerber
发明人： Jeffrey A. Shields , Kent D. Hewitt , Donald S. Gerber
IPC分类号： G11C16/04
CPC分类号： G11C16/0416 , G11C16/12 , G11C16/16 , G11C16/3427 , H01L27/0207 , H01L27/115 , H01L27/11803
摘要： A method for programming and erasing an array of NMOS electrically erasable programmable read only memory (EEPROM) cells that minimizes bit disturbances and high voltage requirements for the memory array cells and supporting circuits. In addition, the array of N-channel memory cells may be separated into independently programmable memory segments by creating multiple, electrically isolated P-wells upon which the memory segments are fabricated. The multiple, electrically isolated P-wells may be created, for example, by p-n junction isolation or dielectric isolation.
摘要翻译：一种用于编程和擦除NMOS电可擦除可编程只读存储器（EEPROM）单元的阵列的方法，其最小化存储器阵列单元和支持电路的位干扰和高电压要求。此外，N沟道存储单元的阵列可以通过产生多个电隔离的P阱来分离成独立可编程的存储器段，在其上制造存储器段。多个电隔离的P阱可以例如通过p-n结隔离或电介质隔离来产生。

3. 发明授权

US07817474B2 Method for programming and erasing an array of NMOS EEPROM cells that minimizes bit disturbances and voltage withstand requirements for the memory array and supporting circuits 有权
标题翻译：用于编程和擦除NMOS EEPROM单元阵列的方法，可最大限度地减少存储器阵列和支持电路的位干扰和电压耐受要求
公开(公告)号：US07817474B2
公开(公告)日：2010-10-19
申请号：US12331542
申请日：2008-12-10
申请人： Jeffrey A. Shields , Kent D. Hewitt , Donald S. Gerber
发明人： Jeffrey A. Shields , Kent D. Hewitt , Donald S. Gerber
IPC分类号： G11C16/00
CPC分类号： G11C16/0416 , G11C16/12 , G11C16/16 , G11C16/3427 , H01L27/0207 , H01L27/115 , H01L27/11803
摘要： A method for programming and erasing an array of NMOS electrically erasable programmable read only memory (EEPROM) cells that minimizes bit disturbances and high voltage requirements for the memory array cells and supporting circuits. In addition, the array of N-channel memory cells may be separated into independently programmable memory segments by creating multiple, electrically isolated P-wells upon which the memory segments are fabricated. The multiple, electrically isolated P-wells may be created, for example, by p-n junction isolation or dielectric isolation.
摘要翻译：一种用于编程和擦除NMOS电可擦除可编程只读存储器（EEPROM）单元的阵列的方法，其最小化存储器阵列单元和支持电路的位干扰和高电压要求。此外，N沟道存储单元的阵列可以通过产生多个电隔离的P阱来分离成独立可编程的存储器段，在其上制造存储器段。多个电隔离的P阱可以例如通过p-n结隔离或电介质隔离来产生。

4. 发明申请

US20090122618A1 Method for Programming and Erasing an Array of NMOS EEPROM Cells that Minimizes Bit Disturbances and Voltage Withstand Requirements for the Memory Array and Supporting Circuits 有权
标题翻译：用于编程和擦除阵列的NMOS EEPROM单元的方法，可以最大限度地减少存储器阵列和支持电路的位干扰和耐压要求
公开(公告)号：US20090122618A1
公开(公告)日：2009-05-14
申请号：US12331542
申请日：2008-12-10
申请人： Jeffrey A. Shields , Kent D. Hewitt , Donald S. Gerber
发明人： Jeffrey A. Shields , Kent D. Hewitt , Donald S. Gerber
IPC分类号： G11C16/06
CPC分类号： G11C16/0416 , G11C16/12 , G11C16/16 , G11C16/3427 , H01L27/0207 , H01L27/115 , H01L27/11803
摘要： A method for programming and erasing an array of NMOS electrically erasable programmable read only memory (EEPROM) cells that minimizes bit disturbances and high voltage requirements for the memory array cells and supporting circuits. In addition, the array of N-channel memory cells may be separated into independently programmable memory segments by creating multiple, electrically isolated P-wells upon which the memory segments are fabricated. The multiple, electrically isolated P-wells may be created, for example, by p-n junction isolation or dielectric isolation.
摘要翻译：一种用于编程和擦除NMOS电可擦除可编程只读存储器（EEPROM）单元的阵列的方法，其最小化存储器阵列单元和支持电路的位干扰和高电压要求。此外，N沟道存储单元的阵列可以通过产生多个电隔离的P阱来分离成独立可编程的存储器段，在其上制造存储器段。多个电隔离的P阱可以例如通过p-n结隔离或电介质隔离来产生。

5. 发明授权

US06300183B1 Independently programmable memory segments within a PMOS electrically erasable programmable read only memory array achieved by N-well separation and method therefor 有权
标题翻译：通过N阱分离实现的PMOS电可擦除可编程只读存储器阵列中的独立可编程存储器段及其方法
公开(公告)号：US06300183B1
公开(公告)日：2001-10-09
申请号：US09272675
申请日：1999-03-19
申请人： Donald S. Gerber , Randy L. Yach , Kent D. Hewitt , Gianpaolo Spadini
发明人： Donald S. Gerber , Randy L. Yach , Kent D. Hewitt , Gianpaolo Spadini
IPC分类号： H01L218238
CPC分类号： H01L27/11521 , G11C16/0416 , H01L27/0207 , H01L27/11519
摘要： An array of P-channel memory cells is separated into independently programmable memory segments by creating multiple, electrically isolated N-wells upon which the memory segments are fabricated. The methods for creating the multiple, electrically isolated N-wells include p-n junction isolation and dielectric isolation.
摘要翻译：通过产生多个电隔离的N阱，将P阵列的P沟道存储单元分成独立的可编程存储器段，在其上制造存储器段。用于产生多个电隔离的N阱的方法包括p-n结隔离和介电隔离。

6. 发明授权

US06504191B2 Independently programmable memory segments within a PMOS electrically erasable programmable read only memory array achieved by N-well separation and method therefor 有权
公开(公告)号：US06504191B2
公开(公告)日：2003-01-07
申请号：US09972563
申请日：2001-10-08
申请人： Donald S. Gerber , Randy L. Yach , Kent D. Hewitt , Gianpaolo Spadini
发明人： Donald S. Gerber , Randy L. Yach , Kent D. Hewitt , Gianpaolo Spadini
IPC分类号： H01L2980
CPC分类号： H01L27/11521 , G11C16/0416 , H01L27/0207 , H01L27/11519
摘要： An array of P-channel memory cells is separated into independently programmable memory segments by creating multiple, electrically isolated N-wells upon which the memory segments are fabricated. The methods for creating the multiple, electrically isolated N-wells include p-n junction isolation and dielectric isolation.

7. 发明授权

US5604701A Initializing a read pipeline of a non-volatile sequential memory device 失效
标题翻译：初始化非易失性顺序存储器件的读取流水线
公开(公告)号：US5604701A
公开(公告)日：1997-02-18
申请号：US508331
申请日：1995-07-27
申请人： Samuel E. Alexander , Kent D. Hewitt
发明人： Samuel E. Alexander , Kent D. Hewitt
IPC分类号： G11C16/06 , G11C7/10 , G11C8/04 , G11C16/20 , G11C16/26 , G11C7/00
CPC分类号： G11C7/106 , G11C16/20 , G11C16/26 , G11C7/1039 , G11C7/1051 , G11C8/04
摘要： A sequential memory device having a read pipeline data structure for reading data from a bitline of a memory array of the device is disclosed. The read pipeline data structure includes at least one data path including a sense amp for sensing the logic level appearing on the bitline, a flip-flop for providing an output signal indicative of the data bits received on the bitline, and means for initializing the data path upon power up of the device such that the first data bit from the memory array is available for output from the device without the need and before the occurrence of a clock signal.
摘要翻译：公开了一种具有用于从设备的存储器阵列的位线读取数据的读流水线数据结构的顺序存储器件。读取流水线数据结构包括至少一个数据路径，包括用于感测出现在位线上的逻辑电平的读出放大器，用于提供表示在位线上接收的数据位的输出信号的触发器，以及初始化数据的装置使得来自存储器阵列的第一数据位可用于从设备输出而不需要并且在时钟信号出现之前的路径。

8. 发明授权

US5488711A Serial EEPROM device and associated method for reducing data load time using a page mode write cache 失效
标题翻译：串行EEPROM器件及相关方法，可通过页面模式写入缓存来减少数据加载时间
公开(公告)号：US5488711A
公开(公告)日：1996-01-30
申请号：US41076
申请日：1993-04-01
申请人： Kent D. Hewitt , Samuel E. Alexander , Richard J. Fisher
发明人： Kent D. Hewitt , Samuel E. Alexander , Richard J. Fisher
IPC分类号： G06F12/08 , G06F13/28 , G11C7/10 , G11C7/22 , G11C16/10 , G06F13/36 , G11C16/04
CPC分类号： G11C16/102 , G06F12/0802 , G06F13/28 , G11C16/10 , G11C7/1021 , G11C7/22
摘要： A serial EEPROM (electrically erasable programmable read only memory) device and method for reducing the time required to load data into the serial EEPROM device using a special write cache are disclosed. The EEPROM has an internal memory array for receiving a burst of data sent by a microcontroller. Data in the burst of data is initially loaded into an SRAM (static random access memory) write cache where it is stored sequentially and grouped in a plurality of pages, so that the bus and the microcontroller are freed to allow the microcontroller to perform other processing tasks at least until the EEPROM memory is written and the EEPROM is again accessible to the microcontroller. Writing of the internal memory array is accomplished sequentially with data from the pages of the cache loaded into rows of the internal memory array until the cache is depleted, the pages being sized so that an integral number of pages is stored in each row of the internal memory array.
摘要翻译：公开了一种串行EEPROM（电可擦除可编程只读存储器）装置和方法，用于减少使用特殊写高速缓存将数据装入串行EEPROM装置所需的时间。 EEPROM具有用于接收由微控制器发送的数据脉冲串的内部存储器阵列。数据突发中的数据最初被加载到SRAM（静态随机存取存储器）写入高速缓存中，其中它被顺序地存储并分组在多个页面中，使得总线和微控制器被释放以允许微控制器执行其他处理任务至少直到写入EEPROM存储器，并且微控制器再次访问EEPROM。内部存储器阵列的写入是从缓存的页面顺序地完成的，该数据被加载到内部存储器阵列的行中，直到高速缓存耗尽，这些页面的大小使得整数个页面被存储在内部的每行中内存阵列

9. 发明授权

US5363334A Write protection security for memory device 失效
标题翻译：为存储设备写保护安全
公开(公告)号：US5363334A
公开(公告)日：1994-11-08
申请号：US41068
申请日：1993-04-10
申请人： Samuel E. Alexander , Richard J. Fisher , Kent D. Hewitt
发明人： Samuel E. Alexander , Richard J. Fisher , Kent D. Hewitt
IPC分类号： G06F12/14 , G11C7/24 , G11C16/22 , G11C7/00
CPC分类号： G11C16/22 , G06F12/1441 , G11C7/24
摘要： An erasable programmable memory device has a number of contiguous data storage cells forming the data memory of the device. The address of one of these data storage cells is stored to designate it as a cell which is to be write protected so that its contents may not thereafter be erased or overwritten. Information is also stored to identify the total number of contiguous data storage cells to be similarly write protected commencing with the cell whose address is stored to designate write protection. The contents of the designated and identified cells are then made permanent. Write protection of the designated and identified cells is accomplished by comparing each write operation address with the addresses of the data storage cells encompassed within the protected area, and if it is within that area, aborting the write operation.
摘要翻译：可擦除可编程存储器件具有形成器件的数据存储器的多个连续的数据存储单元。存储这些数据存储单元之一的地址以将其指定为要被写保护的单元，使得其内容之后不能被擦除或覆盖。还存储信息以识别从存储地址的单元开始以指定写保护的类似写保护的连续数据存储单元的总数。然后将指定和识别的细胞的内容物永久化。通过将每个写入操作地址与保护区域中包含的数据存储单元的地址进行比较，并且如果在该区域内，则中止写入操作来实现指定和识别的单元的写保护。

10. 发明授权

US5367484A Programmable high endurance block for EEPROM device 失效
标题翻译：用于EEPROM器件的可编程高耐久性块
公开(公告)号：US5367484A
公开(公告)日：1994-11-22
申请号：US41642
申请日：1993-04-01
申请人： Samuel E. Alexander , Stephen V. Drehobl , Richard J. Fisher , Leonard F. French , Kent D. Hewitt
发明人： Samuel E. Alexander , Stephen V. Drehobl , Richard J. Fisher , Leonard F. French , Kent D. Hewitt
IPC分类号： G11C16/10 , G11C16/34 , G11C29/00 , G11C11/34
CPC分类号： G11C29/74 , G11C16/10 , G11C16/349 , G11C16/3495
摘要： An erasable programmable memory device has a number of data storage blocks. Each block has an endurance characteristic that at least roughly defines the number of times data may be erased from and written to the block before it wears out in that data cannot then be further erased from and written to the block. A redundant data storage block of memory capacity and endurance similar to that of each of the other data storage blocks is disposed in parallel with a selected one of the latter for which higher endurance is desired. This enables identical data to be written simultaneously to the two blocks and thus considerably increases the endurance of the selected block by virtue of the fact that identical memory cells in both blocks must fail before the endurance of the selected block will be depleted. After the selected block has been designated for high endurance and placed in parallel with the redundant block, a fuse may be set to prevent alteration of that designation.
摘要翻译：可擦除可编程存储器件具有多个数据存储块。每个块具有耐久性特征，其至少粗略地定义数据在其磨损之前被擦除并写入块的次数，然后不能再从块中进一步擦除和写入块。与其他数据存储块中的每一个类似的存储器容量和耐久性的冗余数据存储块与期望更高耐久性的选择的一个并行设置。这使得能够将相同的数据同时写入两个块，并且因此通过两个块中的相同存储器单元在所选块的耐久性将被耗尽之前必须失效的事实显着增加所选块的耐久性。在所选块被指定为高耐久性并且与冗余块并联之后，可以设置保险丝以防止改变该名称。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式