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    • 3. 发明授权
    • Near-field RFID reader antenna
    • 近场RFID阅读器天线
    • US08212679B2
    • 2012-07-03
    • US12507258
    • 2009-07-22
    • Jeong-seok KimWon-kyu ChoiGil-young ChoiJong-suk Chae
    • Jeong-seok KimWon-kyu ChoiGil-young ChoiJong-suk Chae
    • G08B13/14
    • H04Q9/00H01Q1/2216H01Q11/02H04Q2209/47
    • A near-field radio frequency identification (RFID) reader antenna is provided. The near-field RFID reader antenna is intended to separately recognize adjacent items to which a plurality of small RFID tags are attached, such as wines displayed on a shelf in a store or chip trays on casino tables, using a near field. The near-field REID reader antenna includes a dielectric layer, at least one signal line formed on the dielectric layer, a ground surface formed under the dielectric layer, at least one ground line formed under the dielectric layer to be electrically connected to the ground surface in parallel with the signal line, at least one signal stub formed to be electrically connected to the signal line toward the ground line, and at least one ground stub formed to be electrically connected to the ground line toward the signal line in parallel with the signal stub.
    • 提供了近场射频识别(RFID)阅读器天线。 近场RFID读取器天线旨在使用近场来单独识别附接有多个小RFID标签的相邻物品,例如在娱乐场桌上的商店或筹码盘中的货架上显示的葡萄酒。 近场REID读取器天线包括电介质层,形成在电介质层上的至少一条信号线,形成在电介质层下面的接地表面,形成在电介质层之下的至少一个接地线,以电连接到地表面 与信号线并联,至少一个信号短截线形成为电连接到信号线朝向接地线,以及至少一个接地短截线,其形成为与信号线电连接到信号线并与信号 存根。
    • 4. 发明授权
    • Semiconductor memory device and method of manufacturing the same
    • 半导体存储器件及其制造方法
    • US06974986B2
    • 2005-12-13
    • US10367853
    • 2003-02-19
    • Ji-soo KimJeong-seok KimKyoung-sub Shin
    • Ji-soo KimJeong-seok KimKyoung-sub Shin
    • H01L21/768H01L21/8242H01L27/108
    • H01L27/10894H01L27/10814H01L27/10852H01L27/10855H01L27/10885H01L27/10888
    • A semiconductor memory device and manufacturing method, including a bit line connector and a lower electrode connector that respectively connect a bit line and a capacitor lower electrode of the device to active areas of a semiconductor substrate. The connectors are formed using a line-type self-aligned photoresist mask pattern positioned on an interlevel dielectric layer formed on the substrate, which exposes only a portion of the dielectric layer corresponding to a source region and which extends in a direction which a gate electrode extends, to provide a misalignment margin. The bit line connector and the lower electrode connector are respectively formed by one-time mask processes. A contact hole for the bit line connector in a cell area, and a contact hole for a metal wiring plug in a peripheral area are simultaneously formed, alleviating etching burden during subsequent forming of a metal wiring pad.
    • 一种半导体存储器件和制造方法,包括分别将器件的位线和电容器下电极连接到半导体衬底的有源区的位线连接器和下电极连接器。 连接器使用位于衬底上形成的层间电介质层上的线型自对准光致抗蚀剂掩模图案形成,该掩模图案仅暴露与源极区对应的介电层的一部分,并且沿栅极电极 延伸,以提供不对准余量。 位线连接器和下电极连接器分别由一次性掩模处理形成。 同时形成用于单元区域中的位线连接器的接触孔和周边区域中的金属布线插塞的接触孔,从而减轻随后形成金属布线板期间的蚀刻负担。
    • 5. 发明授权
    • Semiconductor memory device and method of manufacturing the same
    • 半导体存储器件及其制造方法
    • US07265051B2
    • 2007-09-04
    • US11241924
    • 2005-10-04
    • Ji-soo KimJeong-seok KimKyoung-sub Shin
    • Ji-soo KimJeong-seok KimKyoung-sub Shin
    • H01L27/108
    • H01L27/10894H01L27/10814H01L27/10852H01L27/10855H01L27/10885H01L27/10888
    • A semiconductor memory device and manufacturing method, including a bit line connector and a lower electrode connector that respectively connect a bit line and a capacitor lower electrode of the device to active areas of a semiconductor substrate. The connectors are formed using a line-type self-aligned photoresist mask pattern positioned on an interlevel dielectric layer formed on the substrate, which exposes only a portion of the dielectric layer corresponding to a source region and which extends in a direction which a gate electrode extends, to provide a misalignment margin. The bit line connector and the lower electrode connector are respectively formed by one-time mask processes. A contact hole for the bit line connector in a cell area, and a contact hole for a metal wiring plug in a peripheral area are simultaneously formed, alleviating etching burden during subsequent forming of a metal wiring pad.
    • 一种半导体存储器件和制造方法,包括分别将器件的位线和电容器下电极连接到半导体衬底的有源区的位线连接器和下电极连接器。 连接器使用位于衬底上形成的层间电介质层上的线型自对准光致抗蚀剂掩模图案形成,该掩模图案仅暴露与源极区对应的介电层的一部分,并且沿栅极电极 延伸,以提供不对准余量。 位线连接器和下电极连接器分别由一次性掩模处理形成。 同时形成用于单元区域中的位线连接器的接触孔和周边区域中的金属布线插塞的接触孔,从而减轻随后形成金属布线板期间的蚀刻负担。
    • 6. 发明授权
    • Semiconductor memory device with a connector for a lower electrode or a bit line
    • 具有用于下电极或位线的连接器的半导体存储器件
    • US06545306B2
    • 2003-04-08
    • US09988679
    • 2001-11-20
    • Ji-soo KimJeong-seok KimKyoung-sub Shin
    • Ji-soo KimJeong-seok KimKyoung-sub Shin
    • H01L27108
    • H01L27/10894H01L27/10814H01L27/10852H01L27/10855H01L27/10885H01L27/10888
    • A semiconductor memory device and manufacturing method, including a bit line connector and a lower electrode connector that respectively connect a bit line and a capacitor lower electrode of the device to active areas of a semiconductor substrate. The connectors are formed using a line-type self-aligned photoresist mask pattern positioned on an interlevel dielectric layer formed on the substrate, which exposes only a portion of the dielectric layer corresponding to a source region and which extends in a direction which a gate electrode extends, to provide a misalignment margin. The bit line connector and the lower electrode connector are respectively formed by one-time mask processes. A contact hole for the bit line connector in a cell area, and a contact hole for a metal wiring plug in a peripheral area are simultaneously formed, alleviating etching burden during subsequent forming of a metal wiring pad.
    • 一种半导体存储器件和制造方法,包括分别将器件的位线和电容器下电极连接到半导体衬底的有源区的位线连接器和下电极连接器。 连接器使用位于衬底上形成的层间电介质层上的线型自对准光致抗蚀剂掩模图案形成,该掩模图案仅暴露与源极区对应的介电层的一部分,并且沿栅极电极 延伸,以提供不对准余量。 位线连接器和下电极连接器分别由一次性掩模处理形成。 同时形成用于单元区域中的位线连接器的接触孔和周边区域中的金属布线插塞的接触孔,从而减轻随后形成金属布线板期间的蚀刻负担。