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1. 发明授权

US08878601B2 Power supply circuit with positive and negative feedback loops 有权
标题翻译：电源电路具有正反馈回路
公开(公告)号：US08878601B2
公开(公告)日：2014-11-04
申请号：US13618290
申请日：2012-09-14
申请人： Jhy-Jyi Sze , Biay-Cheng Hseih , Shou-Gwo Wuu
发明人： Jhy-Jyi Sze , Biay-Cheng Hseih , Shou-Gwo Wuu
IPC分类号： G05F1/10 , G05F1/46
CPC分类号： G05F1/46 , G05F1/10 , G05F3/24 , H01L2924/0002 , H01L2924/00
摘要： A circuit includes a gate node, and a bias circuit coupled to the gate node. The bias circuit is configured to, in response to a change in a gate voltage on the gate node, provide a positive feedback to the gate voltage. A power circuit is coupled to the gate node, wherein the power circuit includes a power Metal-Oxide-Semiconductor (MOS) transistor. The power circuit is configured to, in response to a change in the gate voltage, provide a negative feedback to the gate voltage. An output node is coupled to the power circuit.
摘要翻译：电路包括栅极节点和耦合到栅极节点的偏置电路。偏置电路被配置为响应于栅极节点上的栅极电压的变化，向栅极电压提供正反馈。电源电路耦合到栅极节点，其中电源电路包括功率金属氧化物半导体（MOS）晶体管。电源电路被配置为响应于栅极电压的变化，向栅极电压提供负反馈。输出节点耦合到电源电路。

2. 发明授权

US08735937B2 Fully isolated LIGBT and methods for forming the same 有权
标题翻译：完全隔离的LIGBT及其形成方法
公开(公告)号：US08735937B2
公开(公告)日：2014-05-27
申请号：US13601229
申请日：2012-08-31
申请人： Jhy-Jyi Sze , Biay-Cheng Hseih , Shou-Gwo Wuu
发明人： Jhy-Jyi Sze , Biay-Cheng Hseih , Shou-Gwo Wuu
IPC分类号： H01L29/66 , H01L21/70
CPC分类号： H01L29/66325 , H01L21/265 , H01L21/304 , H01L21/76 , H01L21/761 , H01L21/76224 , H01L29/0696 , H01L29/7393 , H01L29/7394
摘要： A device includes a dielectric layer, and a heavily doped semiconductor layer over the dielectric layer. The heavily doped semiconductor layer is of a first conductivity type. A semiconductor region is over the heavily doped semiconductor layer, wherein the semiconductor region is of a second conductivity type opposite the first conductivity type. A Lateral Insulated Gate Bipolar Transistor (LIGBT) is disposed at a surface of the semiconductor region.
摘要翻译：一种器件包括电介质层和介电层上的重掺杂半导体层。重掺杂半导体层是第一导电类型。半导体区域在重掺杂半导体层之上，其中半导体区域是与第一导电类型相反的第二导电类型。横向绝缘栅双极晶体管（LIGBT）设置在半导体区域的表面。

3. 发明申请

US20130320397A1 Fully Isolated LIGBT and Methods for Forming the Same 有权
公开(公告)号：US20130320397A1
公开(公告)日：2013-12-05
申请号：US13601229
申请日：2012-08-31
申请人： Jhy-Jyi Sze , Biay-Cheng Hseih , Shou-Gwo Wuu
发明人： Jhy-Jyi Sze , Biay-Cheng Hseih , Shou-Gwo Wuu
IPC分类号： H01L29/739 , H01L21/332
CPC分类号： H01L29/66325 , H01L21/265 , H01L21/304 , H01L21/76 , H01L21/761 , H01L21/76224 , H01L29/0696 , H01L29/7393 , H01L29/7394
摘要： A device includes a dielectric layer, and a heavily doped semiconductor layer over the dielectric layer. The heavily doped semiconductor layer is of a first conductivity type. A semiconductor region is over the heavily doped semiconductor layer, wherein the semiconductor region is of a second conductivity type opposite the first conductivity type. A Lateral Insulated Gate Bipolar Transistor (LIGBT) is disposed at a surface of the semiconductor region.

4. 发明申请

US20130321073A1 Power Supply Circuit with Positive and Negative Feedback Loops 有权
标题翻译：具有正反馈回路的电源电路
公开(公告)号：US20130321073A1
公开(公告)日：2013-12-05
申请号：US13618290
申请日：2012-09-14
申请人： Jhy-Jyi Sze , Biay-Cheng Hseih , Shou-Gwo Wuu
发明人： Jhy-Jyi Sze , Biay-Cheng Hseih , Shou-Gwo Wuu
IPC分类号： G05F1/10 , H01L25/00
CPC分类号： G05F1/46 , G05F1/10 , G05F3/24 , H01L2924/0002 , H01L2924/00
摘要： A circuit includes a gate node, and a bias circuit coupled to the gate node. The bias circuit is configured to, in response to a change in a gate voltage on the gate node, provide a positive feedback to the gate voltage. A power circuit is coupled to the gate node, wherein the power circuit includes a power Metal-Oxide-Semiconductor (MOS) transistor. The power circuit is configured to, in response to a change in the gate voltage, provide a negative feedback to the gate voltage. An output node is coupled to the power circuit.
摘要翻译：电路包括栅极节点和耦合到栅极节点的偏置电路。偏置电路被配置为响应于栅极节点上的栅极电压的变化，向栅极电压提供正反馈。电源电路耦合到栅极节点，其中电源电路包括功率金属氧化物半导体（MOS）晶体管。电源电路被配置为响应于栅极电压的变化，向栅极电压提供负反馈。输出节点耦合到电源电路。

5. 发明授权

US08994082B2 Transistors, methods of manufacturing thereof, and image sensor circuits with reduced RTS noise 有权
标题翻译：晶体管，其制造方法和具有减少的RTS噪声的图像传感器电路
公开(公告)号：US08994082B2
公开(公告)日：2015-03-31
申请号：US13250856
申请日：2011-09-30
申请人： Feng-Chi Hung , Jhy-Jyi Sze , Shou-Gwo Wuu
发明人： Feng-Chi Hung , Jhy-Jyi Sze , Shou-Gwo Wuu
IPC分类号： H01L31/062 , H01L31/113 , H01L21/265 , H01L29/78 , H01L27/146 , H01L21/28
CPC分类号： H01L27/14616 , H01L21/0223 , H01L21/26506 , H01L21/26586 , H01L21/266 , H01L21/28123 , H01L21/2822 , H01L21/76224 , H01L27/14603 , H01L27/14612 , H01L27/1463 , H01L29/0653 , H01L29/41775 , H01L29/42368 , H01L29/66568 , H01L29/78
摘要： Transistors, methods of manufacturing thereof, and image sensor circuits with reduced random telegraph signal (RTS) noise are disclosed. In one embodiment, a transistor includes a channel disposed between two isolation regions in a workpiece. The channel has edge regions proximate the isolation regions and a central region between the edge regions. The transistor includes a gate dielectric disposed over the channel, and a gate disposed over the gate dielectric. The transistor includes a voltage threshold modification feature proximate the edge regions configured to increase a voltage threshold of the transistor proximate edge regions relative to the central region of the channel.
摘要翻译：公开了晶体管，其制造方法和具有减少的随机电报信号（RTS）噪声的图像传感器电路。在一个实施例中，晶体管包括设置在工件中的两个隔离区域之间的通道。通道具有靠近隔离区域的边缘区域和边缘区域之间的中心区域。晶体管包括设置在通道上方的栅极电介质和设置在栅极电介质上的栅极。晶体管包括靠近边缘区域的电压阈值修改特征，其被配置成相对于通道的中心区域增加晶体管的边缘区域的电压阈值。

6. 发明授权

US07776676B2 Fabricating method of complementary metal-oxide-semiconductor (CMOS) image sensor including p type gate structure 失效
标题翻译：包括p型栅极结构的互补金属氧化物半导体（CMOS）图像传感器的制造方法
公开(公告)号：US07776676B2
公开(公告)日：2010-08-17
申请号：US11954194
申请日：2007-12-11
申请人： Jhy-Jyi Sze
发明人： Jhy-Jyi Sze
IPC分类号： H01L21/8238
CPC分类号： H01L27/14643 , H01L27/14689
摘要： A method of fabricating a complementary metal-oxide-semiconductor image sensor is provided. First, a substrate having a photo sensitive region and a transistor device region is provided. A p type well in the substrate of the transistor device region is formed. A dielectric layer and an un-doped polysilicon layer on the substrate are sequentially formed. A n type polysilicon layer on a first portion of the transistor device region and a p type polysilicon layer on the photo sensitive region and on a second portion of the transistor device region are formed. The dielectric layer, the n type polysilicon layer and the p type polysilicon layer are patterned to form a plurality of n type gate structures and a p type gate structure on the p type well of the transistor device region. A photo sensitive diode is formed in the substrate of the photo sensitive region.
摘要翻译：提供一种制造互补金属氧化物半导体图像传感器的方法。首先，提供具有光敏区域和晶体管器件区域的衬底。形成在晶体管器件区域的衬底中的p型阱。依次形成基板上的介质层和未掺杂多晶硅层。形成晶体管器件区域的第一部分上的n型多晶硅层和在光敏区域和晶体管器件区域的第二部分上的p型多晶硅层。图案化电介质层，n型多晶硅层和p型多晶硅层，以在晶体管器件区域的p型阱上形成多个n型栅极结构和p型栅极结构。光敏二极管形成在感光区的基板中。

7. 发明申请

US20100073528A1 METHOD OF GENERATING A GAIN OF AN IMAGE FRAME 有权
标题翻译：产生图像帧增益的方法
公开(公告)号：US20100073528A1
公开(公告)日：2010-03-25
申请号：US12236492
申请日：2008-09-23
申请人： Yuan-Che Lee , Jhy-Jyi Sze , Chiao-Fu Chang , Tsung-Chien Wu
发明人： Yuan-Che Lee , Jhy-Jyi Sze , Chiao-Fu Chang , Tsung-Chien Wu
IPC分类号： H04N5/52 , H04N5/20
CPC分类号： H04N5/365 , H04N5/243
摘要： A method of generating a gain of an image frame according to a look up table of gain which is set up based on luminance sensitivity of human eyes is proposed. The method includes setting a gain of an image frame to 1, scanning images of a plurality of front rows of the image frame, averaging the images of the plurality of the front rows of the image frame to generate an average value of the images of the plurality of the front rows of the image frame, finding a gain from the look up table of gain according to the average value of the images of the plurality of the front rows of the image frame, and adjusting remaining rows of the image frame according to the gain to generate images of the remaining rows of the image frame.
摘要翻译：提出了根据基于人眼的亮度灵敏度设置的增益查找表生成图像帧的增益的方法。该方法包括将图像帧的增益设置为1，扫描图像帧的多个前排的图像，对图像帧的多个前行的图像进行平均，以生成图像的图像的平均值多个图像帧的前排，根据图像帧的多个前排的图像的平均值，从增益的查找表中找到增益，并根据图像帧的剩余行调整生成图像帧的剩余行的图像的增益。

8. 发明申请

US20090261393A1 COMPOSITE TRANSFER GATE AND FABRICATION THEREOF 审中-公开
标题翻译：复合传输闸门及其制造方法
公开(公告)号：US20090261393A1
公开(公告)日：2009-10-22
申请号：US12105514
申请日：2008-04-18
申请人： Jhy-Jyi Sze
发明人： Jhy-Jyi Sze
IPC分类号： H01L31/00 , H01L21/00
CPC分类号： H01L21/823842 , H01L21/82345 , H01L27/14603 , H01L27/14643 , H01L27/14689
摘要： A composite transfer gate is described, which is disposed over a semiconductor substrate between an electron reservoir and a floating node in the semiconductor substrate. The composite transfer gate includes at least one N-type portion and a P-type portion that are arranged laterally.
摘要翻译：描述了复合传输门，其被布置在半导体衬底中的电子存储器和半导体衬底中的浮动节点之间。复合传送门包括横向布置的至少一个N型部分和P型部分。

9. 发明申请

US20080113477A1 FABRICATING METHOD OF COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) IMAGE SENSOR 失效
标题翻译：补充金属氧化物半导体（CMOS）图像传感器的制造方法
公开(公告)号：US20080113477A1
公开(公告)日：2008-05-15
申请号：US11954194
申请日：2007-12-11
申请人： Jhy-Jyi Sze
发明人： Jhy-Jyi Sze
IPC分类号： H01L21/8238
CPC分类号： H01L27/14643 , H01L27/14689
摘要： A complementary metal-oxide-semiconductor (CMOS) image sensor including a substrate, a p type well, a light emitting diode, a p type gate structure and a plurality of n type gate structures is provided. The substrate has a photo sensitive region and a transistor device region, and the p type well is disposed in the substrate. The light emitting diode is disposed in the p type well and the substrate of the photo sensitive region. The p type gate structure is disposed on the substrate of the transistor device region. The n type gate structures are disposed on the substrate of the transistor device region.
摘要翻译：提供了包括基板，p型阱，发光二极管，p型栅极结构和多个n型栅极结构的互补金属氧化物半导体（CMOS）图像传感器。衬底具有光敏区域和晶体管器件区域，p型阱设置在衬底中。发光二极管设置在p型阱和光敏区的基板中。 p型栅极结构设置在晶体管器件区域的衬底上。 n型栅极结构设置在晶体管器件区域的衬底上。

10. 发明授权

US07371599B2 Image sensor and method of forming the same 有权
标题翻译：图像传感器及其形成方法
公开(公告)号：US07371599B2
公开(公告)日：2008-05-13
申请号：US11379053
申请日：2006-04-17
申请人： Jhy-Jyi Sze
发明人： Jhy-Jyi Sze
IPC分类号： H01L21/00
CPC分类号： H01L27/14643 , H01L27/14632 , H01L27/14687 , H01L27/14689
摘要： An image sensor includes a semiconductor substrate, a photo receiving area in the semiconductor substrate, a gate electrode installed in a lateral side of the photo receiving area on the semiconductor substrate, and a patterned dielectric layer covering the gate electrode, the photo receiving area, and exposing a partial gate electrode. A spacer surrounds the gate electrode on the dielectric layer.
摘要翻译：图像传感器包括半导体衬底，半导体衬底中的光接收区域，安装在半导体衬底上的光接收区域的横向侧的栅极电极以及覆盖栅电极的图案化电介质层，光接收区域，并露出部分栅电极。间隔物围绕电介质层上的栅电极。

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