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1. 发明申请

US20120294169A1 SYSTEM AND METHOD FOR REDUCING OVERHEAD OF SEARCHER TASKS FOR DISCONTINUOUS RECEPTION 有权
标题翻译：用于不连续接收的搜索器任务的减少的系统和方法
公开(公告)号：US20120294169A1
公开(公告)日：2012-11-22
申请号：US13290033
申请日：2011-11-04
申请人： Jimmy C. Chui , An-swol C. Hu , Jittra Jootar , Feng Lu , Yi Su
发明人： Jimmy C. Chui , An-swol C. Hu , Jittra Jootar , Feng Lu , Yi Su
IPC分类号： H04W24/00 , H04W52/02
CPC分类号： H04W52/0274 , H04W52/02 , H04W52/028 , H04W52/14 , Y02D70/00 , Y02D70/1224 , Y02D70/1242 , Y02D70/1244 , Y02D70/1246 , Y02D70/1262 , Y02D70/1264 , Y02D70/142 , Y02D70/144 , Y02D70/146 , Y02D70/164 , Y02D70/24 , Y02D70/25
摘要： At least one feature pertains to a method of communication that comprises aligning a measurement task that utilizes a resource within a user equipment, such that at least a portion of the measurement task is performed during a time that the resource is enabled in the user equipment, and executing the measurement task during the time that the resource is enabled in the user equipment. In one example, the measurement task may be a searcher task, the resource may comprise receiver circuitry, and the time that the resource is enabled corresponds to a DRX monitoring interval of a downlink channel, such as a high speed shared control channel. By aligning and executing the searcher task during the time that the resource is enabled in the user equipment, searcher overhead may be reduced. Reducing searcher overhead allows the user equipment to save power by disabling the receiver circuitry.
摘要翻译：至少一个特征涉及一种通信方法，包括对齐利用用户设备内的资源的测量任务，使得在用户设备中启用资源的时间期间执行测量任务的至少一部分，并在用户设备中启用资源的时间内执行测量任务。在一个示例中，测量任务可以是搜索者任务，资源可以包括接收机电路，并且资源被启用的时间对应于诸如高速共享控制信道的下行链路信道的DRX监视间隔。通过在用户设备中启用资源的时间内对齐和执行搜索者任务，可以减少搜索者开销。减少搜索器开销允许用户设备通过禁用接收器电路来节省电力。

2. 发明授权

US09113416B2 System and method for reducing overhead of searcher tasks for discontinuous reception 有权
标题翻译：用于减少不连续接收的搜索者任务的开销的系统和方法
公开(公告)号：US09113416B2
公开(公告)日：2015-08-18
申请号：US13290033
申请日：2011-11-04
申请人： Jimmy C. Chui , An-swol C. Hu , Jittra Jootar , Feng Lu , Yi Su
发明人： Jimmy C. Chui , An-swol C. Hu , Jittra Jootar , Feng Lu , Yi Su
IPC分类号： G08C17/00 , H04W52/02 , H04W52/14
CPC分类号： H04W52/0274 , H04W52/02 , H04W52/028 , H04W52/14 , Y02D70/00 , Y02D70/1224 , Y02D70/1242 , Y02D70/1244 , Y02D70/1246 , Y02D70/1262 , Y02D70/1264 , Y02D70/142 , Y02D70/144 , Y02D70/146 , Y02D70/164 , Y02D70/24 , Y02D70/25
摘要： At least one feature pertains to a method of communication that comprises aligning a measurement task that utilizes a resource within a user equipment, such that at least a portion of the measurement task is performed during a time that the resource is enabled in the user equipment, and executing the measurement task during the time that the resource is enabled in the user equipment. In one example, the measurement task may be a searcher task, the resource may comprise receiver circuitry, and the time that the resource is enabled corresponds to a DRX monitoring interval of a downlink channel, such as a high speed shared control channel. By aligning and executing the searcher task during the time that the resource is enabled in the user equipment, searcher overhead may be reduced. Reducing searcher overhead allows the user equipment to save power by disabling the receiver circuitry.
摘要翻译：至少一个特征涉及一种通信方法，包括对齐利用用户设备内的资源的测量任务，使得在用户设备中启用资源的时间期间执行测量任务的至少一部分，并在用户设备中启用资源的时间内执行测量任务。在一个示例中，测量任务可以是搜索者任务，资源可以包括接收机电路，并且资源被启用的时间对应于诸如高速共享控制信道的下行链路信道的DRX监视间隔。通过在用户设备中启用资源的时间内对齐和执行搜索者任务，可以减少搜索者开销。减少搜索器开销允许用户设备通过禁用接收器电路来节省电力。

3. 发明授权

US09257375B2 Multi-die semiconductor package 有权
标题翻译：多芯片半导体封装
公开(公告)号：US09257375B2
公开(公告)日：2016-02-09
申请号：US13236931
申请日：2011-09-20
申请人： Anup Bhalla , Yi Su , David Grey
发明人： Anup Bhalla , Yi Su , David Grey
IPC分类号： H01L23/495 , H01L23/31 , H01L23/00
CPC分类号： H01L25/074 , H01L23/3171 , H01L23/49562 , H01L23/49575 , H01L24/06 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/83 , H01L25/50 , H01L29/7827 , H01L2224/02166 , H01L2224/04026 , H01L2224/04042 , H01L2224/0603 , H01L2224/06181 , H01L2224/291 , H01L2224/2919 , H01L2224/32145 , H01L2224/32148 , H01L2224/32245 , H01L2224/45014 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48145 , H01L2224/48247 , H01L2224/48257 , H01L2224/48465 , H01L2224/49111 , H01L2224/49112 , H01L2224/49175 , H01L2224/49431 , H01L2224/73215 , H01L2224/73265 , H01L2224/83805 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01322 , H01L2924/12032 , H01L2924/13091 , H01L2924/30101 , H01L2924/30107 , H01L2924/00 , H01L2924/3512 , H01L2924/00014 , H01L2924/00012
摘要： A multi-die package has a plurality of leads and first and second semiconductor dies in superimposition and bonded together defining a die stack. The die stack has opposed first and second sides, with each of the first and second semiconductor dies having gate, drain and source regions, and gate, drain and source contacts. The first opposed side has the drain contact of the second semiconductor die, which is in electrical communication with a first set of the plurality of leads. The gate, drain and source contacts of the first semiconductor die and the gate and source contacts of the second semiconductor die are disposed on the second of said opposed sides and in electrical communication with a second set of the plurality of leads. The lead for the source of the first semiconductor die may be the same as the lead for the drain of the second semiconductor die.
摘要翻译：多管芯封装具有多个引线，第一和第二半导体管芯叠加并结合在一起，形成管芯堆叠。管芯堆叠具有相对的第一和第二面，其中第一和第二半导体管芯中的每一个具有栅极，漏极和源极区以及栅极，漏极和源极接触。第一相对侧具有与第一组多个引线电连通的第二半导体管芯的漏极接触。第一半导体管芯的栅极，漏极和源极接触以及第二半导体管芯的栅极和源极触点设置在所述相对侧的第二侧上并且与第二组多个引线电连通。用于第一半导体管芯的源极的引线可以与第二半导体管芯的漏极引线相同。

4. 发明授权

US08994101B2 Shielded gate trench MOS with improved source pickup layout 有权
标题翻译：屏蔽栅极MOS MOS，具有改进的源拾取布局
公开(公告)号：US08994101B2
公开(公告)日：2015-03-31
申请号：US13865941
申请日：2013-04-18
申请人： Hong Chang , Yi Su , Wenjun Li , Limin Weng , Jongoh Kim , John Chen
发明人： Hong Chang , Yi Su , Wenjun Li , Limin Weng , Gary Chen , Jongoh Kim , John Chen
IPC分类号： H01L29/772 , H01L29/78 , H01L27/088 , H01L21/283 , H01L29/40 , H01L29/417 , H01L29/66 , H01L29/732 , H01L29/423 , H01L21/265 , H01L29/45 , H01L29/49 , H01L29/10
CPC分类号： H01L29/7811 , H01L21/26586 , H01L21/283 , H01L27/088 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/41741 , H01L29/4236 , H01L29/42368 , H01L29/42372 , H01L29/4238 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7813 , H01L29/7827
摘要： A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.
摘要翻译：一种制造半导体器件的方法包括使用第一掩模形成多个沟槽。沟槽包括位于终端区域外部和两个相邻有效区域之间的源拾取沟槽。使用第二掩模形成由中间介电区分隔的第一和第二导电区域。使用第三掩模形成到第一导电区域的第一电接触和到第二导电区域的第二电接触，并形成源极金属区域。使用第四掩模形成与栅极金属区域的接触。半导体器件包括位于端子区域外部并位于器件的有源区域外部的源极拾取触点。

5. 发明申请

US20140151790A1 APPROACH TO INTEGRATE SCHOTTKY IN MOSFET 有权
标题翻译：在MOSFET中整合肖特基的方法
公开(公告)号：US20140151790A1
公开(公告)日：2014-06-05
申请号：US13873017
申请日：2013-04-29
申请人： Sik Lui , Yi Su , Daniel Ng , Anup Bhalla
发明人： Sik Lui , Yi Su , Daniel Ng , Anup Bhalla
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7806 , H01L27/0629 , H01L29/0619 , H01L29/0623 , H01L29/1095 , H01L29/41766 , H01L29/66734 , H01L29/7813 , H01L29/872 , H01L29/8725
摘要： An integrated structure combines field effect transistors and a Schottky diode. Trenches formed into a substrate composition extend along a depth of the substrate composition forming mesas therebetween. Each trench is filled with conductive material separated from the trench walls by dielectric material forming a gate region. Two first conductivity type body regions inside each mesa form wells partly into the depth of the substrate composition. An exposed portion of the substrate composition separates the body regions. Second conductivity type source regions inside each body region are adjacent to and on opposite sides of each well. Schottky barrier metal inside each well forms Schottky junctions at interfaces with exposed vertical sidewalls of the exposed portion of the substrate composition separating the body regions.
摘要翻译：集成结构结合了场效应晶体管和肖特基二极管。形成衬底组合物的沟槽沿其中形成台面的衬底组合物的深度延伸。每个沟槽填充有导电材料，该导电材料通过形成栅极区域的电介质材料与沟槽壁分离。每个台面形状内部的两个第一导电类型体区部分地沉积到基底组合物的深度中。衬底组合物的暴露部分分离身体区域。每个身体区域内的第二导电类型源区域与每个孔的相邻侧和相邻侧相邻。每个孔内的肖特基势垒金属在分离体区的基底组合物的暴露部分的暴露的垂直侧壁的界面处形成肖特基结。

6. 发明授权

US08709893B2 Method of making a low-Rdson vertical power MOSFET device 有权
标题翻译：制造低Rdson垂直功率MOSFET器件的方法
公开(公告)号：US08709893B2
公开(公告)日：2014-04-29
申请号：US13216122
申请日：2011-08-23
申请人： Yi Su , Daniel Ng , Anup Bhalla , Jun Lu
发明人： Yi Su , Daniel Ng , Anup Bhalla , Jun Lu
IPC分类号： H01L29/78
CPC分类号： H01L29/7811 , H01L21/30604 , H01L21/30608 , H01L23/495 , H01L23/49503 , H01L23/49513 , H01L23/49562 , H01L24/29 , H01L24/83 , H01L29/0619 , H01L29/0638 , H01L29/0657 , H01L29/0886 , H01L29/41741 , H01L29/41766 , H01L29/456 , H01L29/66666 , H01L29/66727 , H01L29/66734 , H01L29/7802 , H01L29/7813 , H01L29/7827 , H01L2224/291 , H01L2224/2929 , H01L2224/293 , H01L2224/32245 , H01L2224/8309 , H01L2224/83141 , H01L2224/83365 , H01L2224/83385 , H01L2224/83801 , H01L2224/83851 , H01L2924/12036 , H01L2924/12042 , H01L2924/13091 , H01L2924/00014 , H01L2924/014 , H01L2924/00
摘要： The invention relates to a power semiconductor device and its preparation methods thereof. Particularly, the invention aims at providing a method for reducing substrate contribution to the Rdson (drain-source on resistance) of power MOSFETs, and a power MOSFET device made by the method. By forming one or more bottom grooves at the bottom of Si substrate, the on resistance of the power MOSFET device attributed to the substrate is effectively reduced. A matching lead frame base complementary to the substrate with bottom grooves further improves the package of the power MOSFET device.
摘要翻译：本发明涉及功率半导体器件及其制备方法。特别地，本发明旨在提供一种降低功率MOSFET的Rdson（漏源电阻）的基板贡献的方法以及通过该方法制造的功率MOSFET器件。通过在Si衬底的底部形成一个或多个底部沟槽，有效地降低归因于衬底的功率MOSFET器件的导通电阻。与具有底槽的衬底互补的匹配引线框架底座进一步改善了功率MOSFET器件的封装。

7. 发明授权

US08526319B2 Reporting of channel quality indicators for a non-linear detector 失效
标题翻译：报告非线性检测器的通道质量指标
公开(公告)号：US08526319B2
公开(公告)日：2013-09-03
申请号：US12910609
申请日：2010-10-22
申请人： Yi Su , Jia Tang , Atul A. Salvekar , Lei Xiao , Gokhan Mergen , Jonathan Sidi
发明人： Yi Su , Jia Tang , Atul A. Salvekar , Lei Xiao , Gokhan Mergen , Jonathan Sidi
IPC分类号： H04L12/26
CPC分类号： H04L1/0025 , H04B7/0632 , H04B7/0634 , H04L1/0003 , H04L1/0026 , H04L1/0036 , H04L1/06 , H04L1/203 , H04L25/03178 , H04L25/03974 , H04L2025/03808
摘要： Techniques for determining channel quality indicators (CQIs) for a non-linear detector at a user equipment (UE) are described. In one design, the UE may determine at least one parameter (e.g., at least one threshold) based on at least one constellation constrained capacity function. Each threshold may correspond to a maximum number of information bits for one stream when a particular modulation order is used for another stream. The UE may determine CQIs for multiple streams for the non-linear detector based on the at least one parameter. The UE may also select a precoding matrix (e.g., jointly with the CQIs) based on the at least one parameter. The UE may report the selected precoding matrix and the CQIs for the multiple streams. The UE may thereafter receive a transmission of the multiple streams, which may be transmitted based on the selected precoding matrix and the CQIs.
摘要翻译：描述用于确定在用户设备（UE）处的非线性检测器的信道质量指示符（CQI）的技术。在一种设计中，UE可以基于至少一个星座约束容量功能来确定至少一个参数（例如，至少一个阈值）。当特定调制阶数用于另一个流时，每个阈值可以对应于一个流的最大信息比特数。 UE可以基于至少一个参数来确定用于非线性检测器的多个流的CQI。 UE还可以基于至少一个参数来选择预编码矩阵（例如，与CQI共同）。 UE可以针对多个流报告所选择的预编码矩阵和CQI。然后，UE可以接收可以基于所选择的预编码矩阵和CQI发送的多个流的传输。

8. 发明授权

US08431470B2 Approach to integrate Schottky in MOSFET 有权
标题翻译：将肖特基集成在MOSFET中的方法
公开(公告)号：US08431470B2
公开(公告)日：2013-04-30
申请号：US13079675
申请日：2011-04-04
申请人： Sik Lui , Yi Su , Daniel Ng , Anup Bhalla
发明人： Sik Lui , Yi Su , Daniel Ng , Anup Bhalla
IPC分类号： H01L21/28 , H01L21/02
CPC分类号： H01L29/7806 , H01L27/0629 , H01L29/0619 , H01L29/0623 , H01L29/1095 , H01L29/41766 , H01L29/66734 , H01L29/7813 , H01L29/872 , H01L29/8725
摘要： An integrated structure combines field effect transistors and a Schottky diode. Trenches formed into a substrate composition extend along a depth of the substrate composition forming mesas therebetween. Each trench is filled with conductive material separated from the trench walls by dielectric material forming a gate region. Two first conductivity type body regions inside each mesa form wells partly into the depth of the substrate composition. An exposed portion of the substrate composition separates the body regions. Second conductivity type source regions inside each body region are adjacent to and on opposite sides of each well. Schottky barrier metal inside each well forms Schottky junctions at interfaces with exposed vertical sidewalls of the exposed portion of the substrate composition separating the body regions.
摘要翻译：集成结构结合了场效应晶体管和肖特基二极管。形成衬底组合物的沟槽沿其中形成台面的衬底组合物的深度延伸。每个沟槽填充有导电材料，该导电材料通过形成栅极区域的电介质材料与沟槽壁分离。每个台面形状内部的两个第一导电类型体区部分地沉积到基底组合物的深度中。衬底组合物的暴露部分分离身体区域。每个身体区域内的第二导电类型源区域与每个孔的相邻侧和相邻侧相邻。每个孔内的肖特基势垒金属在分离体区的基底组合物的暴露部分的暴露的垂直侧壁的界面处形成肖特基结。

9. 发明授权

US08431457B2 Method for fabricating a shielded gate trench MOS with improved source pickup layout 有权
标题翻译：用于制造具有改进的源拾取布局的屏蔽栅沟槽MOS的方法
公开(公告)号：US08431457B2
公开(公告)日：2013-04-30
申请号：US12722384
申请日：2010-03-11
申请人： Hong Chang , Yi Su , Wenjun Li , Limin Weng , Gary Chen , Jongoh Kim , John Chen
发明人： Hong Chang , Yi Su , Wenjun Li , Limin Weng , Gary Chen , Jongoh Kim , John Chen
IPC分类号： H01L21/027 , H01L29/78
CPC分类号： H01L29/7811 , H01L21/26586 , H01L21/283 , H01L27/088 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/41741 , H01L29/4236 , H01L29/42368 , H01L29/42372 , H01L29/4238 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7813 , H01L29/7827
摘要： A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.
摘要翻译：一种制造半导体器件的方法包括使用第一掩模形成多个沟槽。沟槽包括位于终端区域外部和两个相邻有效区域之间的源拾取沟槽。使用第二掩模形成由中间介电区分隔的第一和第二导电区域。使用第三掩模形成到第一导电区域的第一电接触和到第二导电区域的第二电接触，并形成源极金属区域。使用第四掩模形成与栅极金属区域的接触。半导体器件包括位于端子区域外部并位于器件的有源区域外部的源极拾取触点。

10. 发明申请

US20130069163A1 MULTI-DIE PACKAGE 有权
标题翻译：多模包装
公开(公告)号：US20130069163A1
公开(公告)日：2013-03-21
申请号：US13236931
申请日：2011-09-20
申请人： Anup Bhalla , Yi Su , David Grey
发明人： Anup Bhalla , Yi Su , David Grey
IPC分类号： H01L25/07 , H01L21/60 , H01L25/00
CPC分类号： H01L25/074 , H01L23/3171 , H01L23/49562 , H01L23/49575 , H01L24/06 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/83 , H01L25/50 , H01L29/7827 , H01L2224/02166 , H01L2224/04026 , H01L2224/04042 , H01L2224/0603 , H01L2224/06181 , H01L2224/291 , H01L2224/2919 , H01L2224/32145 , H01L2224/32148 , H01L2224/32245 , H01L2224/45014 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48145 , H01L2224/48247 , H01L2224/48257 , H01L2224/48465 , H01L2224/49111 , H01L2224/49112 , H01L2224/49175 , H01L2224/49431 , H01L2224/73215 , H01L2224/73265 , H01L2224/83805 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01322 , H01L2924/12032 , H01L2924/13091 , H01L2924/30101 , H01L2924/30107 , H01L2924/00 , H01L2924/3512 , H01L2924/00014 , H01L2924/00012
摘要： A multi-die package has a plurality of leads and first and second semiconductor dies in superimposition and bonded together defining a die stack. The die stack has opposed first and second sides, with each of the first and second semiconductor dies having gate, drain and source regions, and gate, drain and source contacts. The first opposed side has the drain contact of the second semiconductor die, which is in electrical communication with a first set of the plurality of leads. The gate, drain and source contacts of the first semiconductor die and the gate and source contacts of the second semiconductor die are disposed on the second of said opposed sides and in electrical communication with a second set of the plurality of leads. The lead for the source of the first semiconductor die may be the same as the lead for the drain of the second semiconductor die.
摘要翻译：多管芯封装具有多个引线，第一和第二半导体管芯叠加并结合在一起，形成管芯堆叠。管芯堆叠具有相对的第一和第二面，其中第一和第二半导体管芯中的每一个具有栅极，漏极和源极区以及栅极，漏极和源极接触。第一相对侧具有与第一组多个引线电连通的第二半导体管芯的漏极接触。第一半导体管芯的栅极，漏极和源极接触以及第二半导体管芯的栅极和源极触点设置在所述相对侧的第二侧上并且与第二组多个引线电连通。用于第一半导体管芯的源极的引线可以与第二半导体管芯的漏极引线相同。

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