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1. 发明申请

US20050220237A1 Method and arrangement for sampling 审中-公开
标题翻译：取样方法和布置
公开(公告)号：US20050220237A1
公开(公告)日：2005-10-06
申请号：US11096071
申请日：2005-03-31
申请人： Harald Sandner , Joerg Goller
发明人： Harald Sandner , Joerg Goller
IPC分类号： G01R31/319 , H03L7/081 , H03L7/091 , H04B3/46 , H04L7/033 , H04L7/04
CPC分类号： H03L7/0814 , G01R31/31922 , H03L7/091 , H04L7/0337
摘要： In the proposed method of sampling data that are related to a clock signal, a three test samples are taken from the same data at positions in time spaced from each other by fixed delays by shifting the clock signal in time with respect to the data until the test samples taken from the same data have an identical value. A shifted clock signal is used to take validated samples of the data. Since the clock is shifted in time in relation to the data so that all test samples have an identical value, that value is the true value of a datum sampled within a period of time from the moment of the first test sample to the moment of the last test sample, and a validated data sample is obtained.
摘要翻译：在所提出的与时钟信号相关的数据采样方法中，通过固定的延迟通过相对于数据在时间上移动时钟信号而在相互间隔的位置处从相同的数据中获取三个测试样本，直到从相同数据获取的测试样本具有相同的值。移位的时钟信号用于取得经过验证的数据样本。由于时钟相对于数据在时间上移位，所以所有的测试样本都具有相同的值，该值是从第一个测试样本到当前时刻的一段时间内采样的数据的真实值获得最后一个测试样本，并获得经过验证的数据样本。

2. 发明授权

US07660364B2 Method of transmitting serial bit-stream and electronic transmitter for transmitting a serial bit-stream 有权
标题翻译：发送串行比特流的方法和用于发送串行比特流的电子发射机
公开(公告)号：US07660364B2
公开(公告)日：2010-02-09
申请号：US11384731
申请日：2006-03-20
申请人： Harald Sandner , Joerg Goller
发明人： Harald Sandner , Joerg Goller
IPC分类号： H04L27/00
CPC分类号： H04L25/0288 , H04L25/497
摘要： The present invention relates to an electronic transmitter for serially transmitting bit sequences. The electronic transmitter includes a detection device 10 and a transmitting device 12. The detection device 10 is adapted to detect a predefined bit sequence for transmittal. The predefined bit sequence is susceptible to inter-symbol-interference. The transmitting device 12 is adapted to transmit serially the detected predefined bit sequence in such a way, that a duration for transmittal of a particular bit in said predefined bit sequence is longer than a duration of transmittal of remaining bits in said predefined bit sequence.
摘要翻译：本发明涉及一种串行发送比特序列的电子发射机。电子发射机包括检测装置10和发送装置12.检测装置10适于检测用于发送的预定义比特序列。预定义的位序列易受符号间干扰的影响。发送设备12适于以这样的方式串行地发送检测到的预定义比特序列，即所述预定义比特序列中的特定比特的发送持续时间长于所述预定义比特序列中剩余比特的传送持续时间。

3. 发明申请

US20070069927A1 Method of transmitting a serial bit-stream and electronic transmitter for transmitting a serial bit-stream 有权
标题翻译：发送用于发送串行比特流的串行比特流和电子发射机的方法
公开(公告)号：US20070069927A1
公开(公告)日：2007-03-29
申请号：US11384731
申请日：2006-03-20
申请人： Harald Sandner , Joerg Goller
发明人： Harald Sandner , Joerg Goller
IPC分类号： H03M9/00
CPC分类号： H04L25/0288 , H04L25/497
摘要： The present invention relates to an electronic transmitter for serially transmitting bit sequences. The electronic transmitter includes a detection device 10 and a transmitting device 12. The detection device 10 is adapted to detect a predefined bit sequence for transmittal. The predefined bit sequence is susceptible to inter-symbol-interference. The transmitting device 12 is adapted to transmit serially the detected predefined bit sequence in such a way, that a duration for transmittal of a particular bit in said predefined bit sequence is longer than a duration of transmittal of remaining bits in said predefined bit sequence.
摘要翻译：本发明涉及一种串行发送比特序列的电子发射机。电子发射机包括检测装置10和发送装置12.检测装置10适于检测用于发送的预定义比特序列。预定义的位序列易受符号间干扰的影响。发送设备12适于以这样的方式串行地发送检测到的预定义比特序列，即所述预定义比特序列中的特定比特的发送持续时间长于所述预定义比特序列中剩余比特的传送持续时间。

4. 发明申请

US20070063880A1 Highspeed serial transmission system and a method for reducing jitter in data transfer on such a system 审中-公开
标题翻译：高速串行传输系统和减少这种系统上的数据传输抖动的方法
公开(公告)号：US20070063880A1
公开(公告)日：2007-03-22
申请号：US11384600
申请日：2006-03-20
申请人： Joerg Goller , Harald Sandner
发明人： Joerg Goller , Harald Sandner
IPC分类号： H03M9/00
CPC分类号： H03K5/1565 , H04L1/205 , H04L7/0025 , H04L25/03343
摘要： In a high-speed serial transmission system (10) comprising a transmitter (12), a transmission line (14) and a receiver (16), the transmitter (12) includes a bit-stream generator (18) for generating a predetermined pseudo random bit sequence (PRBS), and a controllable phase distortion circuit (20) having an input (24) connected to the bit-stream generator (18) and a signal output (26) connected to the transmission line (14). The receiver (16) includes a sampling circuit (30) with a signal input (36) connected to the transmission line (14), a sampling clock input (38) and a data output (40), a clock recovery circuit (32) with a phase-locked loop circuit (42) and a controllable phase interpolator (44) that has signal inputs (45) connected to signal outputs of the phase-locked loop circuit (42) and an output (48) connected to the sampling clock input (38) of the sampling circuit (30), and a bit-stream verification circuit (32) with an input (50) connected to the data output (40) of the sampling circuit (30) and an output (52) that controls the controllable phase interpolator. An output (54) of the bit-stream verification circuit (34) controls the controllable phase distortion circuit (20) in the transmitter (12) in response to a bit error rate (BER) detected in the bit-stream received form the data output (40) of the sampling circuit (30) by comparison with the predetermined pseudo random bit sequence (PRBS).
摘要翻译：在包括发射机（12），传输线（14）和接收机（16）的高速串行传输系统（10）中，发射器（12）包括位流发生器（18），用于产生预定的伪随机比特序列（PRBS）和具有连接到比特流发生器（18）的输入（24）和连接到传输线（14）的信号输出（26）的可控相位失真电路（20）。接收器（16）包括具有连接到传输线（14）的信号输入（36），采样时钟输入（38）和数据输出（40），时钟恢复电路（32）的采样电路（30）具有锁相环电路（42）和可控相位内插器（44），其具有连接到锁相环电路（42）的信号输出的信号输入（45）和连接到采样时钟的输出（48）采样电路（30）的输入（38）和连接到采样电路（30）的数据输出（40）的输入（50）的位流验证电路（32）和输出（52），控制可控相位内插器。比特流验证电路（34）的输出（54）响应于从数据接收的比特流中检测到的比特误码率（BER）来控制发射机（12）中的可控相位失真电路（20）通过与预定伪随机比特序列（PRBS）进行比较，采样电路（30）的输出（40）。

5. 发明申请

US20050201191A1 Data synchronization arrangement 有权
公开(公告)号：US20050201191A1
公开(公告)日：2005-09-15
申请号：US11071673
申请日：2005-03-03
申请人： Joerg Goller , Norbert Reichel
发明人： Joerg Goller , Norbert Reichel
IPC分类号： G06F1/12 , G06F13/38 , G11C8/00
CPC分类号： G06F1/12 , G06F1/3203 , G06F2213/0038 , G11C8/04 , Y02D10/126
摘要： A data synchronization arrangement is provided that is fail-safe at high speed and low power consumption, for exchanging clocked data between different clock domains running in a digital processing equipment at the same clock frequency but at an arbitrary relative phase shift. A register arrangement has a predetermined number of parallel registers, each register having a data input, a write clock input, a read clock input and a data output. A write select multiplexer has an input receiving a write clock signal from a first clock domain, one clock output for each of the parallel registers and connected to a write clock input of a respective register, and one write select input for each clock output. A read select multiplexer has an input receiving a read clock signal from a second clock domain, one clock output for each of the parallel registers and connected to a read clock input of a respective register, and one read select input for each clock output. A write select shift register has a number of stages corresponding to the predetermined number of registers and an output stage looped back to an input stage. Each stage of the write select shift register has an output connected to a respective one of the write select inputs of the write select multiplexer. The write select shift register is clocked with the write clock signal. A read select shift register has a number of stages corresponding to the predetermined number of registers and an output stage looped back to an input stage. Each stage of the read shift register has an output connected to a respective one of the read select inputs of the read select multiplexer. The read select shift register is clocked with the read clock signal. A reset circuit for initializes each shift register with a bit pattern that contains only one high value, the bit patterns in the shift registers having a constant relative offset. In operation, a clocked data input stream synchronized with the clock of the first clock domain is applied to the data inputs of the registers and a clocked data output stream synchronized with the clock of the second clock domain is taken from the data outputs of the registers.

6. 发明授权

US07668022B2 Integrated circuit for clock generation for memory devices 有权
标题翻译：用于存储器件时钟生成的集成电路
公开(公告)号：US07668022B2
公开(公告)日：2010-02-23
申请号：US12110684
申请日：2008-04-28
申请人： Joerg Goller
发明人： Joerg Goller
IPC分类号： G11C7/10
CPC分类号： G11C7/10 , G11C7/22 , G11C7/222
摘要： A device for generating clock signals for use with a plurality of DDR memory devices on a dual in-line memory module (DIMM) board is provided that has a data buffer for buffering data. A clock divider divides a first clock signal (CLK1) having a first clock frequency to generate a second clock signal (CLK20) having a second clock frequency which is an integer multiple of the first clock frequency. A shift register (SH) receives the second clock signal as a data input signal, and comprises a plurality flip-flops having clock inputs coupled to receive the first clock signal (CLK1), and further coupled so that the data output of a preceding flip-flop is coupled to be the data input of a following flip-flop. The second clock signal is shifted through the shift register (SH) in response to the first clock signal (CLK1) to generate a plurality of shifted clock signals (CLK 21, . . . , CLK32) at respective data outputs of the plurality of flip-flops. A multiplexer commonly coupled to the data outputs of the flip-flops selects one of the shifted clock signals (CLK 21, . . . , CLK32) to serve as an output clock signal for transmission of the buffered data to a memory device.
摘要翻译：提供了一种用于在双列直插存储器模块（DIMM）板上产生与多个DDR存储器设备一起使用的时钟信号的装置，其具有用于缓冲数据的数据缓冲器。时钟分频器分割具有第一时钟频率的第一时钟信号（CLK1）以产生具有作为第一时钟频率的整数倍的第二时钟频率的第二时钟信号（CLK20）。移位寄存器（SH）接收第二时钟信号作为数据输入信号，并且包括具有被耦合以接收第一时钟信号（CLK1）的时钟输入的多个触发器，并进一步耦合，使得先前翻转的数据输出 -flop被耦合为以下触发器的数据输入。响应于第一时钟信号（CLK1），第二时钟信号通过移位寄存器（SH）移位，以在多个翻转的相应数据输出端产生多个移位的时钟信号（CLK 21，...，CLK32） -flops。通常耦合到触发器的数据输出的多路复用器选择一个移位的时钟信号（CLK 21，...，CLK32）作为输出时钟信号，用于将缓冲的数据传输到存储器件。

7. 发明申请

US20050201163A1 Data synchronization arrangement 有权
公开(公告)号：US20050201163A1
公开(公告)日：2005-09-15
申请号：US11074443
申请日：2005-03-08
申请人： Norbert Reichel , Joerg Goller
发明人： Norbert Reichel , Joerg Goller
IPC分类号： G06F1/12 , G06F5/06 , G06F5/10 , G06F13/40 , H04L7/00 , G11C5/00
CPC分类号： G06F1/12 , G06F5/10 , G06F13/4059 , H04L7/0008 , H04L7/005
摘要： A data synchronization arrangement is provided that is fail-safe and allows high-speed operation. Clocked data are exchanged between different clock domains running in a digital processing equipment at the same clock frequency but at an arbitrary relative phase shift. The data synchronization arrangement comprises a buffer memory with a predetermined limited number of memory locations each of which has a data write port and a data read port. A write select multiplexer has a data input receiving an input data stream synchronized with the clock from a first clock domain, one data output for each of said memory locations and connected to a respective data write port, and one write select input for each data output. A read select multiplexer has one data input for each of the memory locations and connected to a respective data read port, one read select input for each data input, and a data output supplying an output data stream synchronized with the clock from a second clock domain. A write select shift register has a number of stages corresponding to the predetermined number of memory locations and an output stage looped back to an input stage, each stage having an output connected to a respective one of the write select inputs of the write select multiplexer. The write select shift register is clocked with the clock from the first clock domain. A read select shift register has a number of stages corresponding to the predetermined number of memory locations, each stage having an output connected to a respective one of the read select inputs of the read select multiplexer. The read select shift register is clocked with the clock from the second clock domain. A bit synchronization circuit is provided for loading each shift register with a bit pattern that contains only one high logic value, the bit patterns in the shift registers having a relative offset. In operation, a data input stream synchronized with the clock of the first clock domain is applied to the data input of the write select multiplexer and a data output stream synchronized with the clock of the second clock domain is taken from the data output of the read select multiplexer.

8. 发明申请

US20080265967A1 INTEGRATED CIRCUIT FOR CLOCK GENERATION FOR MEMORY DEVICES 有权
标题翻译：用于存储器件的时钟产生的集成电路
公开(公告)号：US20080265967A1
公开(公告)日：2008-10-30
申请号：US12110684
申请日：2008-04-28
申请人： Joerg Goller
发明人： Joerg Goller
IPC分类号： G06F1/04
CPC分类号： G11C7/10 , G11C7/22 , G11C7/222
摘要： A device for generating clock signals for use with a plurality of DDR memory devices on a dual in-line memory module (DIMM) board is provided that has a data buffer for buffering data. A clock divider divides a first clock signal (CLK1) having a first clock frequency to generate a second clock signal (CLK20) having a second clock frequency which is an integer multiple of the first clock frequency. A shift register (SH) receives the second clock signal as a data input signal, and comprises a plurality flip-flops having clock inputs coupled to receive the first clock signal (CLK1), and further coupled so that the data output of a preceding flip-flop is coupled to be the data input of a following flip-flop. The second clock signal is shifted through the shift register (SH) in response to the first clock signal (CLK1) to generate a plurality of shifted clock signals (CLK 21, . . . , CLK32) at respective data outputs of the plurality of flip-flops. A multiplexer commonly coupled to the data outputs of the flip-flops selects one of the shifted clock signals (CLK 21, . . . , CLK32) to serve as an output clock signal for transmission of the buffered data to a memory device.
摘要翻译：提供了一种用于在双列直插存储器模块（DIMM）板上产生与多个DDR存储器设备一起使用的时钟信号的装置，其具有用于缓冲数据的数据缓冲器。时钟分频器分割具有第一时钟频率的第一时钟信号（CLK 1），以产生具有第二时钟频率的第二时钟信号（CLK 20），第二时钟信号是第一时钟频率的整数倍。移位寄存器（SH）接收第二时钟信号作为数据输入信号，并且包括具有耦合以接收第一时钟信号（CLK 1）的时钟输入的多个触发器，并进一步耦合，使得前一个的数据输出触发器耦合为以下触发器的数据输入。响应于第一时钟信号（CLK 1），第二时钟信号通过移位寄存器（SH）移位，以在多个数据输出端产生多个移位的时钟信号（CLK 21，...，CLK 32）的触发器。通常耦合到触发器的数据输出的多路复用器选择移位的时钟信号（CLK 21，...，CLK 32）中的一个作为用于将缓冲的数据传输到存储器件的输出时钟信号。

9. 发明授权

US07369068B2 Method of recovering digital data from a clocked serial input signal and clocked data recovery circuit 有权
标题翻译：从时钟串行输入信号和时钟数据恢复电路中恢复数字数据的方法
公开(公告)号：US07369068B2
公开(公告)日：2008-05-06
申请号：US11374929
申请日：2006-03-14
申请人： Joerg Goller , Antonio Priego
发明人： Joerg Goller , Antonio Priego
IPC分类号： H03M7/00
CPC分类号： G06F13/4291 , H03L7/07 , H03L7/0814 , H03L7/0996 , H04L7/0025 , H04L7/005 , H04L7/0331
摘要： Digital data are recovered from a clocked serial input signal. The input signal is sampled with a sampling clock signal supplied by a first phase interpolator to obtain a sampled digital signal. The first phase interpolator is controlled with a voting circuit to adjust the phase of the sampling clock relative to the eye in the eye-diagram of the input signal. The first phase interpolator has signal inputs connected to signal outputs of a voltage controlled oscillator in a phase-locked loop circuit that has a reference signal input to which the reference clock signal is applied. The sampled digital signal is written to a single-bit FIFO buffer with a write clock signal that has the same timing as the sampling clock. A filtered output signal is read from the FIFO buffer with a read clock signal supplied by a second phase interpolator that has signal inputs connected to the signal outputs of the voltage controlled oscillator in the phase-locked loop. The second phase interpolator is controlled with a pointer monitor that monitors the write and read select pointers in the FIFO buffer to adjust the timing of the read clock signal relative to the write clock signal. With this method, the hunting jitter is filtered out while a frequency offset is still allowed between the reference clock and the data signal.
摘要翻译：数字数据从时钟串行输入信号中恢复。用由第一相位内插器提供的采样时钟信号对输入信号进行采样，以获得采样的数字信号。用投票电路控制第一相位内插器，以在输入信号的眼图中调整采样时钟相对于眼睛的相位。第一相位内插器具有连接到锁相环电路中的压控振荡器的信号输出的信号输入，该锁相环电路具有被施加基准时钟信号的参考信号输入。采样数字信号被写入具有与采样时钟相同定时的写时钟信号的单位FIFO缓冲器。从FIFO缓冲器读出经过滤波的输出信号，其中读取时钟信号由第二相位内插器提供，该信号输入端连接到锁相环中压控振荡器的信号输出端。用指针监视器控制第二相位内插器，该监视器监视FIFO缓冲器中的写入和读取选择指针，以调整读取时钟信号相对于写入时钟信号的定时。利用这种方法，在参考时钟和数据信号之间仍然允许频率偏移的情况下，滤除了抖动抖动。

10. 发明授权

US07145831B2 Data synchronization arrangement 有权
标题翻译：数据同步安排
公开(公告)号：US07145831B2
公开(公告)日：2006-12-05
申请号：US11071673
申请日：2005-03-03
申请人： Joerg Goller , Norbert Reichel
发明人： Joerg Goller , Norbert Reichel
IPC分类号： G11C8/00
CPC分类号： G06F1/12 , G06F1/3203 , G06F2213/0038 , G11C8/04 , Y02D10/126
摘要： A data synchronization arrangement is provided that is fail-safe at high speed and low power consumption, for exchanging clocked data between different clock domains running in a digital processing equipment at the same clock frequency but at an arbitrary relative phase shift. A register arrangement has a predetermined number of parallel registers, each register having a data input, a write clock input, a read clock input and a data output. A write select multiplexer has an input receiving a write clock signal from a first clock domain, one clock output for each of the parallel registers and connected to a write clock input of a respective register, and one write select input for each clock output. A read select multiplexer has an input receiving a read clock signal from a second clock domain, one clock output for each of the parallel registers and connected to a read clock input of a respective register, and one read select input for each clock output. A write select shift register has a number of stages corresponding to the predetermined number of registers and an output stage looped back to an input stage.
摘要翻译：提供了在高速和低功耗下故障安全的数据同步装置，用于在以相同的时钟频率但在任意相对相移的数字处理设备中运行的不同时钟域之间交换时钟数据。寄存器布置具有预定数量的并行寄存器，每个寄存器具有数据输入，写时钟输入，读时钟输入和数据输出。写选择多路复用器具有接收来自第一时钟域的写入时钟信号的输入，对于每个并行寄存器的一个时钟输出并连接到相应寄存器的写入时钟输入，以及每个时钟输出的一个写入选择输入。读选择多路复用器具有接收来自第二时钟域的读取时钟信号的输入，每个并行寄存器的一个时钟输出并连接到相应寄存器的读取时钟输入，以及每个时钟输出的一个读取选择输入。写选择移位寄存器具有与预定数量的寄存器相对应的级数，以及循环回到输入级的输出级。

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