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1. 发明授权

US08755213B2 Decoding scheme for bipolar-based diode three-dimensional memory requiring bipolar programming 失效
标题翻译：需要双极性编程的双极型二极管三维存储器的解码方案
公开(公告)号：US08755213B2
公开(公告)日：2014-06-17
申请号：US13407848
申请日：2012-02-29
申请人： John K. DeBrosse , Kailash Gopalakrishnan , Chung H. Lam , Jing Li
发明人： John K. DeBrosse , Kailash Gopalakrishnan , Chung H. Lam , Jing Li
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0069 , G11C5/025 , G11C8/10 , G11C8/14 , G11C11/16 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0014 , G11C13/0023 , G11C2013/0071 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/77
摘要： A system and method for operating a bipolar memory cell array including a bidirectional access diode. The system includes a column voltage. The column voltage switch includes column voltages and an output electrically coupled to the bidirectional access diode. The column voltages include at least one write-one column voltage and at least one write-zero column voltage. The system also includes a row voltage switch. The row voltage switch includes row voltages and an output electrically coupled to the bidirectional access diode. The row voltages include at least one write-one row voltage and at least one write-zero row voltage. The system further includes a column decoder and a row decoder electrically coupled to a select line of the column voltage switch and row voltage switch, respectively. The system includes a write driver electrically coupled to the select lines of the row and column switches.
摘要翻译：一种用于操作包括双向存取二极管的双极存储单元阵列的系统和方法。该系统包括列电压。列电压开关包括列电压和电耦合到双向存取二极管的输出。列电压包括至少一个写一列电压和至少一个写零列电压。该系统还包括行电压开关。行电压开关包括行电压和电耦合到双向存取二极管的输出。行电压包括至少一个写入一行电压和至少一个写入零行电压。该系统还包括分别与列电压开关和行电压开关的选择线电耦合的列解码器和行解码器。该系统包括电耦合到行和列开关的选择线的写入驱动器。

2. 发明申请

US20130223125A1 DECODING SCHEME FOR BIPOLAR-BASED DIODE THREE-DIMENSIONAL MEMORY REQUIRING BIPOLAR PROGRAMMING 失效
标题翻译：用于双极二极管的解码方案三维存储器需要双极性编程
公开(公告)号：US20130223125A1
公开(公告)日：2013-08-29
申请号：US13407848
申请日：2012-02-29
申请人： John K. DeBrosse , Kailash Gopalakrishnan , Chung H. Lam , Jing Li
发明人： John K. DeBrosse , Kailash Gopalakrishnan , Chung H. Lam , Jing Li
IPC分类号： G11C11/00 , G11C7/10 , G11C7/00
CPC分类号： G11C13/0069 , G11C5/025 , G11C8/10 , G11C8/14 , G11C11/16 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0014 , G11C13/0023 , G11C2013/0071 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/77
摘要： A system and method for operating a bipolar memory cell array including a bidirectional access diode. The system includes a column voltage. The column voltage switch includes column voltages and an output electrically coupled to the bidirectional access diode. The column voltages include at least one write-one column voltage and at least one write-zero column voltage. The system also includes a row voltage switch. The row voltage switch includes row voltages and an output electrically coupled to the bidirectional access diode. The row voltages include at least one write-one row voltage and at least one write-zero row voltage. The system further includes a column decoder and a row decoder electrically coupled to a select line of the column voltage switch and row voltage switch, respectively. The system includes a write driver electrically coupled to the select lines of the row and column switches.
摘要翻译：一种用于操作包括双向存取二极管的双极存储单元阵列的系统和方法。该系统包括列电压。列电压开关包括列电压和电耦合到双向存取二极管的输出。列电压包括至少一个写一列电压和至少一个写零列电压。该系统还包括行电压开关。行电压开关包括行电压和电耦合到双向存取二极管的输出。行电压包括至少一个写入一行电压和至少一个写入零行电压。该系统还包括分别与列电压开关和行电压开关的选择线电耦合的列解码器和行解码器。该系统包括电耦合到行和列开关的选择线的写入驱动器。

3. 发明授权

US08842491B2 Decoding scheme for bipolar-based diode three-dimensional memory requiring unipolar programming 有权
标题翻译：需要单极编程的双极型二极管三维存储器的解码方案
公开(公告)号：US08842491B2
公开(公告)日：2014-09-23
申请号：US13551597
申请日：2012-07-17
申请人： Kailash Gopalakrishnan , Chung H. Lam , Jing Li , Robert K. Montoye
发明人： Kailash Gopalakrishnan , Chung H. Lam , Jing Li , Robert K. Montoye
IPC分类号： G11C8/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0023 , G11C13/0038 , G11C13/004 , G11C2213/71 , G11C2213/72
摘要： A system and method for operating a unipolar memory cell array including a bidirectional access diode. The system includes a column voltage switch electrically coupled to a plurality of column voltages. The column voltage switch includes an output electrically coupled to the bidirectional access diode. The plurality of column voltages includes at least one select column voltage and one deselect column voltage. The system includes a row voltage switch electrically coupled to a plurality of row voltages. The row voltage switch includes an output electrically coupled to the bidirectional access diode. The plurality of row voltages includes at least one select row voltage and one deselect row voltage. The system includes a column and row decoder electrically coupled to a select line of the column and row voltage switches, respectively.
摘要翻译：一种用于操作包括双向存取二极管的单极存储单元阵列的系统和方法。该系统包括电耦合到多个列电压的列电压开关。列电压开关包括电耦合到双向存取二极管的输出。多个列电压包括至少一个选择列电压和一个取消选择列电压。该系统包括电耦合到多个行电压的行电压开关。行电压开关包括电耦合到双向存取二极管的输出。多个行电压包括至少一个选择行电压和一个取消选择行电压。该系统包括分别电耦合到列的选择线和行电压开关的列和行解码器。

4. 发明授权

US08873271B2 3D architecture for bipolar memory using bipolar access device 有权
标题翻译：使用双极存取器件的双极存储器的3D架构
公开(公告)号：US08873271B2
公开(公告)日：2014-10-28
申请号：US13209405
申请日：2011-08-14
申请人： Chung H. Lam , Jing Li , Kailash Gopalakrishnan
发明人： Chung H. Lam , Jing Li , Kailash Gopalakrishnan
IPC分类号： G11C11/00 , H01L27/24 , H01L45/00 , H01L27/22 , G11C13/00 , G11C7/00 , G11C5/02
CPC分类号： G11C13/00 , G11C5/02 , G11C7/00 , G11C11/16 , G11C11/22 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0014 , G11C13/0023 , G11C13/0069 , G11C2013/0073 , G11C2213/71 , H01L27/224 , H01L27/2409 , H01L45/04 , H01L45/06 , H01L45/146 , H01L45/147 , H01L45/16
摘要： Memory device and method for fabricating a memory device on two layers of a semiconductor wafer. An example device includes bit lines and word lines fabricated at one layer of a semiconductor wafer and re-writable nonvolatile memory cells that include a two-terminal access device with a bidirectional voltage-current characteristics for positive and negative voltages applied at the terminals. Additionally, a drive circuit electrically coupled to the memory cells and configured to program the memory cells is fabricated at another layer of the semiconductor wafer. Another example embodiment includes a memory device where a plurality of memory arrays are fabricated at one layer of a semiconductor wafer and a plurality of drive circuits electrically coupled to the memory cells and configured to read the memory cells are fabricated at a second layer of the semiconductor wafer.
摘要翻译：用于在两层半导体晶片上制造存储器件的存储器件和方法。示例性器件包括在半导体晶片的一个层处制造的位线和字线以及包括具有用于在端子处施加的正电压和负电压的双向电压 - 电流特性的双端子存取器件的可重写非易失性存储器单元。此外，在半导体晶片的另一层处制造电耦合到存储器单元并被配置为对存储器单元进行编程的驱动电路。另一示例性实施例包括存储器件，其中在半导体晶片的一个层处制造多个存储器阵列，并且电耦合到存储器单元并被配置为读取存储器单元的多个驱动电路在半导体的第二层处制造晶圆。

5. 发明申请

US20140022850A1 DECODING SCHEME FOR BIPOLAR-BASED DIODE THREE-DIMENSIONAL MEMORY REQUIRING UNIPOLAR PROGRAMMING 有权
标题翻译：用于双极二极管的三维存储器的解码方案需要单核编程
公开(公告)号：US20140022850A1
公开(公告)日：2014-01-23
申请号：US13551597
申请日：2012-07-17
申请人： Kailash Gopalakrishnan , Chung H. Lam , Jing Li , Robert K. Montoye
发明人： Kailash Gopalakrishnan , Chung H. Lam , Jing Li , Robert K. Montoye
IPC分类号： G11C7/10
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0023 , G11C13/0038 , G11C13/004 , G11C2213/71 , G11C2213/72
摘要： A system and method for operating a unipolar memory cell array including a bidirectional access diode. The system includes a column voltage switch electrically coupled to a plurality of column voltages. The column voltage switch includes an output electrically coupled to the bidirectional access diode. The plurality of column voltages includes at least one select column voltage and one deselect column voltage. The system includes a row voltage switch electrically coupled to a plurality of row voltages. The row voltage switch includes an output electrically coupled to the bidirectional access diode. The plurality of row voltages includes at least one select row voltage and one deselect row voltage. The system includes a column and row decoder electrically coupled to a select line of the column and row voltage switches, respectively.
摘要翻译：一种用于操作包括双向存取二极管的单极存储单元阵列的系统和方法。该系统包括电耦合到多个列电压的列电压开关。列电压开关包括电耦合到双向存取二极管的输出。多个列电压包括至少一个选择列电压和一个取消选择列电压。该系统包括电耦合到多个行电压的行电压开关。行电压开关包括电耦合到双向存取二极管的输出。多个行电压包括至少一个选择行电压和一个取消选择行电压。该系统包括分别电耦合到列的选择线和行电压开关的列和行解码器。

6. 发明授权

US08902690B2 Decoding scheme for bipolar-based diode three-dimensional memory requiring unipolar programming 有权
标题翻译：需要单极编程的双极型二极管三维存储器的解码方案
公开(公告)号：US08902690B2
公开(公告)日：2014-12-02
申请号：US13584423
申请日：2012-08-13
申请人： Kailash Gopalakrishnan , Chung H. Lam , Jing Li , Robert K. Montoye
发明人： Kailash Gopalakrishnan , Chung H. Lam , Jing Li , Robert K. Montoye
IPC分类号： G11C8/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0023 , G11C13/0038 , G11C13/004 , G11C2213/71 , G11C2213/72
摘要： A system and method for operating a unipolar memory cell array including a bidirectional access diode. An example embodiment is a method including determining if the operating state of the unipolar memory cell is in a select state or a deselect state and the programming state is a read state or a write state. The method switches a column voltage switch based on the operating state and the programming state of the unipolar memory cell. The method further switches a row voltage switch based on the operating state and the programming state of the unipolar memory cell.
摘要翻译：一种用于操作包括双向存取二极管的单极存储单元阵列的系统和方法。示例性实施例是一种方法，包括确定单极存储器单元的操作状态是处于选择状态还是取消选择状态，并且编程状态是读取状态或写入状态。该方法根据单极性存储单元的工作状态和编程状态切换列电压开关。该方法还基于单极存储器单元的操作状态和编程状态来切换行电压开关。

7. 发明申请

US20130039110A1 3D ARCHITECTURE FOR BIPOLAR MEMORY USING BIPOLAR ACCESS DEVICE 有权
标题翻译：使用双极性访问设备的双极存储器的3D架构
公开(公告)号：US20130039110A1
公开(公告)日：2013-02-14
申请号：US13209405
申请日：2011-08-14
申请人： Chung H. Lam , Jing Li , Kailash Gopalakrishnan
发明人： Chung H. Lam , Jing Li , Kailash Gopalakrishnan
IPC分类号： G11C5/02 , H01L21/02
CPC分类号： G11C13/00 , G11C5/02 , G11C7/00 , G11C11/16 , G11C11/22 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0014 , G11C13/0023 , G11C13/0069 , G11C2013/0073 , G11C2213/71 , H01L27/224 , H01L27/2409 , H01L45/04 , H01L45/06 , H01L45/146 , H01L45/147 , H01L45/16
摘要： Memory device and method for fabricating a memory device on two layers of a semiconductor wafer. An example device includes bit lines and word lines fabricated at one layer of a semiconductor wafer and re-writable nonvolatile memory cells that include a two-terminal access device with a bidirectional voltage-current characteristics for positive and negative voltages applied at the terminals. Additionally, a drive circuit electrically coupled to the memory cells and configured to program the memory cells is fabricated at another layer of the semiconductor wafer. Another example embodiment includes a memory device where a plurality of memory arrays are fabricated at one layer of a semiconductor wafer and a plurality of drive circuits electrically coupled to the memory cells and configured to read the memory cells are fabricated at a second layer of the semiconductor wafer.
摘要翻译：用于在两层半导体晶片上制造存储器件的存储器件和方法。示例性器件包括在半导体晶片的一个层处制造的位线和字线以及包括具有用于在端子处施加的正电压和负电压的双向电压 - 电流特性的双端子存取器件的可重写非易失性存储器单元。此外，在半导体晶片的另一层处制造电耦合到存储器单元并被配置为对存储器单元进行编程的驱动电路。另一示例性实施例包括存储器件，其中在半导体晶片的一个层处制造多个存储器阵列，并且电耦合到存储器单元并被配置为读取存储器单元的多个驱动电路在半导体的第二层处制造晶圆。

8. 发明申请

US20140022851A1 DECODING SCHEME FOR BIPOLAR-BASED DIODE THREE-DIMENSIONAL MEMORY REQUIRING UNIPOLAR PROGRAMMING 有权
标题翻译：用于双极二极管的三维存储器的解码方案需要单核编程
公开(公告)号：US20140022851A1
公开(公告)日：2014-01-23
申请号：US13584423
申请日：2012-08-13
申请人： Kailash Gopalakrishnan , Chung H. Lam , Jing Li , Robert K. Montoye
发明人： Kailash Gopalakrishnan , Chung H. Lam , Jing Li , Robert K. Montoye
IPC分类号： G11C7/10
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0023 , G11C13/0038 , G11C13/004 , G11C2213/71 , G11C2213/72
摘要： A system and method for operating a unipolar memory cell array including a bidirectional access diode. An example embodiment is a method including determining if the operating state of the unipolar memory cell is in a select state or a deselect state and the programming state is a read state or a write state. The method switches a column voltage switch based on the operating state and the programming state of the unipolar memory cell. The method further switches a row voltage switch based on the operating state and the programming state of the unipolar memory cell.
摘要翻译：一种用于操作包括双向存取二极管的单极存储单元阵列的系统和方法。示例性实施例是一种方法，包括确定单极存储器单元的操作状态是处于选择状态还是取消选择状态，并且编程状态是读取状态或写入状态。该方法根据单极性存储单元的工作状态和编程状态切换列电压开关。该方法还基于单极存储器单元的操作状态和编程状态来切换行电压开关。

9. 发明授权

US08811060B2 Non-volatile memory crosspoint repair 有权
标题翻译：非易失性存储器交叉点修复
公开(公告)号：US08811060B2
公开(公告)日：2014-08-19
申请号：US13485748
申请日：2012-05-31
申请人： Geoffrey W. Burr , Rohit S. Shenoy , Kailash Gopalakrishnan
发明人： Geoffrey W. Burr , Rohit S. Shenoy , Kailash Gopalakrishnan
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0004 , G11C13/003 , G11C17/165
摘要： A device for use with a memory cross-point array of elements, each of which comprises a selection device in series with a state-holding device, in one embodiment includes a controller, configured to apply at least one voltage and/or current pulse to a selected one or more of the elements, said selected one or more of the elements including a partially- or completely-shorted selection device, so that said partially- or completely-shorted selection device passes enough current so as to damage its corresponding state-holding device and place said corresponding state-holding device in a highly resistive state, while any other selection device that is not partially- or completely-shorted passes less current so that the state-holding device corresponding to said other selection device remains unaffected. Additional systems and methods are also presented.
摘要翻译：一种与存储器交叉点阵列元件一起使用的装置，每个元件包括与状态保持装置串联的选择装置，在一个实施例中包括控制器，被配置为将至少一个电压和/或电流脉冲施加到所选择的一个或多个元件，所述选定的一个或多个元件包括部分或完全短路的选择装置，使得所述部分或完全短路的选择装置通过足够的电流，以便损坏其对应的状态 - 并且将所述对应的状态保持装置置于高电阻状态，而没有部分或全部短路的任何其他选择装置通过较少电流，使得与所述其他选择装置对应的状态保持装置保持不受影响。还介绍了其他系统和方法。

10. 发明申请

US20130044532A1 LOW TEMPERATURE BEOL COMPATIBLE DIODE HAVING HIGH VOLTAGE MARGINS FOR USE IN LARGE ARRAYS OF ELECTRONIC COMPONENTS 有权
标题翻译：具有高电压容量的低温BEO兼容二极管用于大型电子元件阵列
公开(公告)号：US20130044532A1
公开(公告)日：2013-02-21
申请号：US13209569
申请日：2011-08-15
申请人： Donald S. Bethune , Kailash Gopalakrishnan , Andrew J. Kellock , Rohit S. Shenoy , Kumar R. Virwani
发明人： Donald S. Bethune , Kailash Gopalakrishnan , Andrew J. Kellock , Rohit S. Shenoy , Kumar R. Virwani
IPC分类号： G11C11/00 , H01L45/00
CPC分类号： H01L29/872 , G11C13/003 , G11C2029/5002 , G11C2029/5006 , G11C2213/72 , H01L27/1021 , H01L27/224 , H01L27/2427 , H01L45/141 , H01L45/1616
摘要： A crystalline semiconductor Schottky barrier-like diode sandwiched between two conducting electrodes is in series with a memory element, a word line and a bit line, wherein the setup provides voltage margins greater than 1V and current densities greater than 5×106 A/cm2. This Schottky barrier-like diode can be fabricated under conditions compatible with low-temperature BEOL semiconductor processing, can supply high currents at low voltages, exhibits high on-off ratios, and enables large memory arrays.
摘要翻译：夹在两个导电电极之间的晶体半导体肖特基势垒状二极管与存储元件，字线和位线串联，其中，该设置提供大于1V的电压裕度和大于5×106A / cm 2的电流密度。这种肖特基势垒状二极管可以在与低温BEOL半导体处理兼容的条件下制造，可以在低电压下提供高电流，具有高开关比，并且可以实现大型存储器阵列。

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