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1. 发明授权

US07421689B2 Processor-architecture for facilitating a virtual machine monitor 失效
标题翻译：处理器架构，便于虚拟机监控
公开(公告)号：US07421689B2
公开(公告)日：2008-09-02
申请号：US10695267
申请日：2003-10-28
申请人： Jonathan K. Ross , Dale Morris , Donald C. Soltis, Jr. , Rohit Bhatia , Eric Delano
发明人： Jonathan K. Ross , Dale Morris , Donald C. Soltis, Jr. , Rohit Bhatia , Eric Delano
IPC分类号： G06F9/455
CPC分类号： G06F9/45533
摘要： Virtual-machine-monitor operation and implementation is facilitated by number of easily implemented features and extensions added to the features of a processor architecture. These features, one or more of which are used in various embodiments of the present invention, include a vmsw instruction that provides a means for transitioning between virtualization mode and non-virtualization mode without an interruption, a virtualization fault that faults on an attempt by a priority-0 routine in virtualization mode attempting to execute a privileged instruction, and a flexible highest-implemented-address mechanism to partition virtual address space into a virtualization address space and a non-virtualization address space.
摘要翻译：虚拟机监视器的操作和实现通过添加到处理器架构的特征中的容易实现的特征和扩展的数量来实现。这些特征，其中一个或多个在本发明的各种实施例中使用，包括提供用于在不中断的情况下在虚拟化模式和非虚拟化模式之间转换的手段的vmsw指令，虚拟化故障，尝试执行特权指令的虚拟化模式中的优先级0例程，以及将虚拟地址空间划分为虚拟化地址空间和非虚拟化地址空间的灵活的最高实现地址机制。

2. 发明申请

US20050091652A1 Processor-architecture for facilitating a virtual machine monitor 失效
标题翻译：处理器架构，便于虚拟机监控
公开(公告)号：US20050091652A1
公开(公告)日：2005-04-28
申请号：US10695267
申请日：2003-10-28
申请人： Jonathan Ross , Dale Morris , Donald Soltis , Rohit Bhatia , Eric Delano
发明人： Jonathan Ross , Dale Morris , Donald Soltis , Rohit Bhatia , Eric Delano
IPC分类号： G06F9/455
CPC分类号： G06F9/45533
摘要： Virtual-machine-monitor operation and implementation is facilitated by number of easily implemented features and extensions added to the features of a processor architecture. These features, one or more of which are used in various embodiments of the present invention, include a vmsw instruction that provides a means for transitioning between virtualization mode and non-virtualization mode without an interruption, a virtualization fault that faults on an attempt by a priority-0 routine in virtualization mode attempting to execute a privileged instruction, and a flexible highest-implemented-address mechanism to partition virtual address space into a virtualization address space and a non-virtualization address space.
摘要翻译：虚拟机监视器的操作和实现通过添加到处理器架构的特征中的容易实现的特征和扩展的数量来实现。这些特征，其中一个或多个在本发明的各种实施例中使用，包括提供用于在不中断的情况下在虚拟化模式和非虚拟化模式之间转换的手段的vmsw指令，虚拟化故障，尝试执行特权指令的虚拟化模式中的优先级0例程，以及将虚拟地址空间划分为虚拟化地址空间和非虚拟化地址空间的灵活的最高实现地址机制。

3. 发明授权

US07281116B2 Multiprocessor system having plural memory locations for respectively storing TLB-shootdown data for plural processor nodes 失效
标题翻译：具有用于分别存储用于多个处理器节点的TLB击落数据的多个存储器位置的多处理器系统
公开(公告)号：US07281116B2
公开(公告)日：2007-10-09
申请号：US10903200
申请日：2004-07-30
申请人： Jonathan K. Ross , Dale Morris
发明人： Jonathan K. Ross , Dale Morris
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F2212/682
摘要： The present invention provides a multiprocessor system and method in which plural memory locations are used for storing TLB-shootdown data respectively for plural processors. In contrast to systems in which a single area of memory serves for all processors' TLB-shootdown data, different processors can describe the memory they want to free concurrently. Thus, concurrent TLB-shootdown request are less likely to result in performance-limiting TLB-shootdown contentions that have previously constrained the scaleability of multiprocessor systems.
摘要翻译：本发明提供一种多处理器系统和方法，其中使用多个存储器位置来分别存储用于多个处理器的TLB击倒数据。与其中单个存储器区域用于所有处理器的TLB击倒数据的系统相反，不同的处理器可以描述他们想要同时释放的存储器。因此，并发的TLB-downdown请求不太可能导致先前限制多处理器系统可扩展性的性能限制TLB击倒争用。

4. 发明授权

US06931515B2 Method and system for using dynamic, deferred operation information to control eager deferral of control-speculative loads 失效
标题翻译：使用动态延迟操作信息来控制控制推测负载的急速推迟的方法和系统
公开(公告)号：US06931515B2
公开(公告)日：2005-08-16
申请号：US10208095
申请日：2002-07-29
申请人： Jonathan K. Ross , Dale Morris
发明人： Jonathan K. Ross , Dale Morris
IPC分类号： G06F9/38 , G06F9/30 , G06F9/312
CPC分类号： G06F9/3865 , G06F9/383 , G06F9/3842
摘要： A method and system for determining, at run-time, whether or not to defer an exception that arises during execution of a control-speculative load instruction based on a recent history of execution of that control-speculative load instruction. The method and system relies on recent execution history stored in a speculative-load-accelerated-deferral table. If an exception arises during execution of a control-speculative load instruction, then the speculative-load-accelerated-deferral table is searched for an entry corresponding to the control-speculative load instruction. If an entry is found, then the exception is deferred, since the speculative-load-accelerated-deferral table indicates that a recent exception arising from execution of the control-speculative load instruction was not recovered via a chk.s-mediated branch to a recovery block, and not otherwise used by a non-speculative instruction. By contrast, if no entry corresponding to the control-speculative load instruction is found in the speculative-load-accelerated-deferral table, then the exception is immediately handled.
摘要翻译：一种方法和系统，用于在运行时确定是否推迟在执行控制推测加载指令期间出现的异常，这是基于该控制推测加载指令的执行的最近历史。该方法和系统依赖于存储在推测加载延迟表中的最近执行历史。如果在执行控制推测加载指令期间出现异常，则搜索推测加载加速延迟表以查找与控制推测加载指令相对应的条目。如果找到条目，则异常被延迟，因为推测加载加速延迟表指示由控制推测加载指令的执行引起的最近异常没有通过chk.s介入的分支恢复到恢复块，而不是由非推测性指令使用。相反，如果在推测加载延迟表中没有找到与控制推测加载指令相对应的条目，则立即处理异常。

5. 发明申请

US20120240116A1 Performance In A Virtualization Architecture With A Processor Abstraction Layer 审中-公开
标题翻译：在具有处理器抽象层的虚拟化架构中的性能
公开(公告)号：US20120240116A1
公开(公告)日：2012-09-20
申请号：US13483307
申请日：2012-05-30
申请人： Hin L. Leung , Amy L. Santoni , Gary N. Hammond , William R. Greene , Kushagra V. Vaid , Dale Morris , Jonathan Ross
发明人： Hin L. Leung , Amy L. Santoni , Gary N. Hammond , William R. Greene , Kushagra V. Vaid , Dale Morris , Jonathan Ross
IPC分类号： G06F9/455 , G06F9/46
CPC分类号： G06F9/45533
摘要： Embodiments of apparatuses and methods for improving performance in a virtualization architecture are disclosed. In one embodiment, an apparatus includes a processor and a processor abstraction layer. The processor abstraction layer includes instructions that, when executed by the processor, support techniques to improve the performance of the apparatus in a virtualization architecture.
摘要翻译：公开了用于提高虚拟化架构中的性能的装置和方法的实施例。在一个实施例中，一种装置包括处理器和处理器抽象层。处理器抽象层包括当由处理器执行时支持技术来提高虚拟化架构中的设备的性能的指令。

6. 发明申请

US20060063177A1 Biomarkers and assays for carcinogenesis 审中-公开
标题翻译：生物标志物和致癌作用的测定
公开(公告)号：US20060063177A1
公开(公告)日：2006-03-23
申请号：US11189064
申请日：2005-07-25
申请人： Roderick Bunch , Dale Morris , Sandra Curtiss , Charles Rodi
发明人： Roderick Bunch , Dale Morris , Sandra Curtiss , Charles Rodi
IPC分类号： C12Q1/68
摘要： The present invention relates to carcinogenesis biomarkers produced by phenobarbitol-treated rat hepatocytes, nucleic acid molecules that encode carcinogenesis biomarkers or a fragment thereof and nucleic acid molecules that are useful as probes or primers for detecting or inducing carcinogenesis, respectively. The invention also relates to applications of the factor or fragment such as forming antibodies capable of binding the carcinogenesis biomarkers or fragments thereof.
摘要翻译：本发明涉及由苯巴比妥治疗的大鼠肝细胞产生的致癌生物标志物，编码致癌生物标志物的核酸分子或其片段，以及可用作探测或诱导癌发生的探针或引物的核酸分子。本发明还涉及因子或片段的应用，例如形成能够结合致癌生物标志物或其片段的抗体。

7. 发明授权

US08214830B2 Performance in a virtualization architecture with a processor abstraction layer 有权
标题翻译：在具有处理器抽象层的虚拟化架构中的性能
公开(公告)号：US08214830B2
公开(公告)日：2012-07-03
申请号：US11041061
申请日：2005-01-19
申请人： Hin L. Leung , Amy L. Santoni , Gary N. Hammond , William R. Greene , Kushagra V. Vaid , Dale Morris , Jonathan Ross
发明人： Hin L. Leung , Amy L. Santoni , Gary N. Hammond , William R. Greene , Kushagra V. Vaid , Dale Morris , Jonathan Ross
IPC分类号： G06F9/46 , G06F9/00 , G06F1/24
CPC分类号： G06F9/45533
摘要： Embodiments of apparatuses and methods for improving performance in a virtualization architecture are disclosed. In one embodiment, an apparatus includes a processor and a processor abstraction layer. The processor abstraction layer includes instructions that, when executed by the processor, support techniques to improve the performance of the apparatus in a virtualization architecture.
摘要翻译：公开了用于提高虚拟化架构中的性能的装置和方法的实施例。在一个实施例中，一种装置包括处理器和处理器抽象层。处理器抽象层包括当由处理器执行时支持技术来提高虚拟化架构中的设备的性能的指令。

8. 发明授权

US07424597B2 Variable reordering (Mux) instructions for parallel table lookups from registers 失效
标题翻译：来自寄存器的并行表查找的可变重排序（Mux）指令
公开(公告)号：US07424597B2
公开(公告)日：2008-09-09
申请号：US10403785
申请日：2003-03-31
申请人： Ruby B. Lee , Dale Morris
发明人： Ruby B. Lee , Dale Morris
IPC分类号： G06F9/312 , G06F9/315
CPC分类号： G06F9/30032 , G06F9/3004
摘要： Parallel table lookups are implemented using variable Mux instructions to reorder data. Table data can be represented in a “table” register, while the desired ordering can be represented in an “Index” register. A direct variable Mux instruction can specify the table register and the index register as arguments, along with a result register. The instruction writes at least some of the data from the table register into the result register as specified in the index register. If the entire table cannot fit within a single register, entries can be divided between two or more table registers. An indirect variable Mux instruction can specify both a table-register-select register and a subword-location-select register. Both the direct and indirect Mux instructions can be used with entry data that is divided in accordance with significance between registers. In that case, plural Mux instructions are used with UnPack instructions that concatenate portions of the table entries.
摘要翻译：使用变量Mux指令实现并行表查找，以重新排序数据。表数据可以在“表”寄存器中表示，而所需的顺序可以在“索引”寄存器中表示。直接变量Mux指令可以指定表寄存器和索引寄存器作为参数，以及结果寄存器。该指令将表寄存器中的至少一些数据写入索引寄存器中指定的结果寄存器。如果整个表不能放在单个寄存器中，则可以在两个或多个表寄存器之间划分条目。间接变量Mux指令可以指定表寄存器选择寄存器和子字选择寄存器。直接和间接MUX指令都可以与根据寄存器之间的重要性划分的条目数据一起使用。在这种情况下，多个Mux指令用于连接表项部分的UnPack指令。

9. 发明申请

US20060064528A1 Privileged resource access 审中-公开
标题翻译：特权资源访问
公开(公告)号：US20060064528A1
公开(公告)日：2006-03-23
申请号：US10944266
申请日：2004-09-17
申请人： Donald Soltis, , Dale Morris
发明人： Donald Soltis, , Dale Morris
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： At least one entry in an original interrupt vector table is replaced with an instruction set to handle access to a privileged resource. An operating system privilege level is modified to one or more resources. Subsequent access to the privileged resource causes an interrupt. Processing of the interrupt is directed to the instruction set to handle access to the privileged resource.
摘要翻译：原始中断向量表中的至少一个条目被替换为处理对特权资源的访问的指令集。操作系统权限级别被修改为一个或多个资源。对特权资源的后续访问会导致中断。中断的处理针对指令集来处理对特权资源的访问。

10. 发明申请

US20060026359A1 Multiprocessor system having plural memory locations for respectively storing TLB-shootdown data for plural processor nodes 失效
标题翻译：具有用于分别存储用于多个处理器节点的TLB击落数据的多个存储器位置的多处理器系统
公开(公告)号：US20060026359A1
公开(公告)日：2006-02-02
申请号：US10903200
申请日：2004-07-30
申请人： Jonathan Ross , Dale Morris
发明人： Jonathan Ross , Dale Morris
IPC分类号： G06F12/00 , G06F12/10
CPC分类号： G06F12/1027 , G06F2212/682
摘要： The present invention provides a multiprocessor system and method in which plural memory locations are used for storing TLB-shootdown data respectively for plural processors. In contrast to systems in which a single area of memory serves for all processors' TLB-shootdown data, different processors can describe the memory they want to free concurrently. Thus, concurrent TLB-shootdown request are less likely to result in performance-limiting TLB-shootdown contentions that have previously constrained the scaleability of multiprocessor systems.
摘要翻译：本发明提供一种多处理器系统和方法，其中使用多个存储器位置来分别存储用于多个处理器的TLB击倒数据。与其中单个存储器区域用于所有处理器的TLB击倒数据的系统相反，不同的处理器可以描述他们想要同时释放的存储器。因此，并发的TLB-downdown请求不太可能导致先前限制多处理器系统可扩展性的性能限制TLB击倒争用。

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