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1. 发明授权

US09348766B2 Balanced P-LRU tree for a “multiple of 3” number of ways cache 有权
标题翻译：平衡的P-LRU树为“多个3”的缓存方式
公开(公告)号：US09348766B2
公开(公告)日：2016-05-24
申请号：US13994690
申请日：2011-12-21
申请人： Adi Basel , Gur Hildesheim , Shlomo Raikin , Robert Chappell , Ho-Seop Kim , Rohit Bhatia
发明人： Adi Basel , Gur Hildesheim , Shlomo Raikin , Robert Chappell , Ho-Seop Kim , Rohit Bhatia
IPC分类号： G06F13/00 , G06F12/12 , G06F3/06 , G06F12/00 , G06F12/08
CPC分类号： G06F12/122 , G06F3/0604 , G06F12/00 , G06F12/0842 , G06F12/0864 , G06F12/124 , G06F12/125
摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing a balanced P-LRU tree for a “multiple of 3” number of ways cache. For example, in one embodiment, such means may include an integrated circuit having a cache and a plurality of ways. In such an embodiment the plurality of ways include a quantity that is a multiple of three and not a power of two, and further in which the plurality of ways are organized into a plurality of pairs. In such an embodiment, means further include a single bit for each of the plurality of pairs, in which each single bit is to operate as an intermediate level decision node representing the associated pair of ways and a root level decision node having exactly two individual bits to point to one of the single bits to operate as the intermediate level decision nodes representing an associated pair of ways. In this exemplary embodiment, the total number of bits is N−1, wherein N is the total number of ways in the plurality of ways. Alternative structures are also presented for full LRU implementation, a “multiple of 5” number of cache ways, and variations of the “multiple of 3” number of cache ways.
摘要翻译：根据本文公开的实施例，提供了用于实现用于“3”倍的方式缓存的平衡P-LRU树的方法，系统，机制，技术和装置。例如，在一个实施例中，这种装置可以包括具有高速缓存和多个方式的集成电路。在这样的实施例中，多个方式包括量是三的倍数而不是二的幂，并且其中多个方式被组织成多对。在这种实施例中，装置还包括用于多个对中的每一对的单个比特，其中每个单个比特将用作表示相关联的一对路由的中间级别决策节点，以及具有正好两个单独比特的根级别决策节点指向要作为表示相关联的方式的中间级决策节点操作的单个位之一。在该示例性实施例中，总数是N-1，其中N是多个方式的总路数。还提供了替代结构，用于完整的LRU实现，“多路复用5”缓存方式，以及“3”倍数缓存方式的变化。

2. 发明授权

US09069690B2 Concurrent page table walker control for TLB miss handling 有权
标题翻译：用于TLB未命中处理的并发页表步行控制
公开(公告)号：US09069690B2
公开(公告)日：2015-06-30
申请号：US13613777
申请日：2012-09-13
申请人： Gur Hildesheim , Chang Kian Tan , Robert S. Chappell , Rohit Bhatia
发明人： Gur Hildesheim , Chang Kian Tan , Robert S. Chappell , Rohit Bhatia
IPC分类号： G06F12/10
CPC分类号： G06F12/10 , G06F12/1027 , G06F2212/1024 , G06F2212/651 , G06F2212/655 , G06F2212/681 , G06F2212/684
摘要： In an embodiment, a page miss handler includes paging caches and a first walker to receive a first linear address portion and to obtain a corresponding portion of a physical address from a paging structure, a second walker to operate concurrently with the first walker, and a logic to prevent the first walker from storing the obtained physical address portion in a paging cache responsive to the first linear address portion matching a corresponding linear address portion of a concurrent paging structure access by the second walker. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，页面未命中处理程序包括寻呼高速缓存和第一步行器，以接收第一线性地址部分并且从寻呼结构获得物理地址的对应部分，与第一步行者并行操作的第二步行者，以及用于防止第一步行器响应于匹配由第二步行者访问的并行寻呼结构的对应线性地址部分的第一线性地址部分而将所获得的物理地址部分存储在寻呼高速缓存器中的逻辑。描述和要求保护其他实施例。

3. 发明授权

US08479029B2 Methods and apparatuses for reducing step loads of processors 失效
公开(公告)号：US08479029B2
公开(公告)日：2013-07-02
申请号：US13167970
申请日：2011-06-24
申请人： Kevin Safford , Rohit Bhatia , Chris Bostak , Richard Blumberg , Blaine Stackhouse , Steve Undy
发明人： Kevin Safford , Rohit Bhatia , Chris Bostak , Richard Blumberg , Blaine Stackhouse , Steve Undy
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3234 , G06F1/3203
摘要： Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.

4. 发明申请

US20110252255A1 Methods And Apparatuses For Reducing Step Loads Of Processors 失效
标题翻译：减少处理器阶跃负载的方法和装置
公开(公告)号：US20110252255A1
公开(公告)日：2011-10-13
申请号：US13167970
申请日：2011-06-24
申请人： Kevin Safford , Rohit Bhatia , Chris Bostak , Richard Blumberg , Blaine Stackhouse , Steve Undy
发明人： Kevin Safford , Rohit Bhatia , Chris Bostak , Richard Blumberg , Blaine Stackhouse , Steve Undy
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3203
摘要： Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.
摘要翻译：公开了减少处理器的步进负载的方法和装置。方法实施例包括检查要由处理器处理的多个指令以确定其具有的指令的类型，基于指令的类型在执行周期中计算功耗，并将执行限制到指令的子集号码来控制执行期间的电量。一些实施例还可以创建人为活动以为处理器提供最小功率层。装置实施例包括用于确定输入指令流中的指令类型的指令类型确定逻辑，用于计算与在执行周期中处理多个指令相关联的功耗的功率计算器，以及通过限制数量来控制功耗的指令限制逻辑的执行期间要处理的指令。

5. 发明授权

US07992017B2 Methods and apparatuses for reducing step loads of processors 有权
标题翻译：减少处理器阶跃负载的方法和装置
公开(公告)号：US07992017B2
公开(公告)日：2011-08-02
申请号：US11900316
申请日：2007-09-11
申请人： Kevin Safford , Rohit Bhatia , Chris Bostak , Richard Blumberg , Blaine Stackhouse , Steve Undy
发明人： Kevin Safford , Rohit Bhatia , Chris Bostak , Richard Blumberg , Blaine Stackhouse , Steve Undy
IPC分类号： G06F1/32 , G06F11/30
CPC分类号： G06F1/3234 , G06F1/3203
摘要： Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.
摘要翻译：公开了减少处理器的步进负载的方法和装置。方法实施例包括检查要由处理器处理的多个指令以确定其具有的指令的类型，基于指令的类型在执行周期中计算功耗，并且将执行限制到指令的子集号码来控制执行期间的电量。一些实施例还可以创建人为活动以为处理器提供最小功率层。装置实施例包括用于确定输入指令流中的指令类型的指令类型确定逻辑，用于计算与在执行周期中处理多个指令相关联的功耗的功率计算器，以及通过限制数量来控制功耗的指令限制逻辑的执行期间要处理的指令。

6. 发明申请

US20140215161A1 BALANCED P-LRU TREE FOR A "MULTIPLE OF 3" NUMBER OF WAYS CACHE 有权
标题翻译：平衡P-LRU树为“多个3”的方式快速访问
公开(公告)号：US20140215161A1
公开(公告)日：2014-07-31
申请号：US13994690
申请日：2011-12-21
申请人： Adi Basel , Gur Hildeshem , Shlomo Raikin , Robert Chappell , Ho-Seop Kim , Rohit Bhatia
发明人： Adi Basel , Gur Hildeshem , Shlomo Raikin , Robert Chappell , Ho-Seop Kim , Rohit Bhatia
IPC分类号： G06F12/12
CPC分类号： G06F12/122 , G06F3/0604 , G06F12/00 , G06F12/0842 , G06F12/0864 , G06F12/124 , G06F12/125
摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing a balanced P-LRU tree for a “multiple of 3” number of ways cache. For example, in one embodiment, such means may include an integrated circuit having a cache and a plurality of ways. In such an embodiment the plurality of ways include a quantity that is a multiple of three and not a power of two, and further in which the plurality of ways are organized into a plurality of pairs. In such an embodiment, means further include a single bit for each of the plurality of pairs, in which each single bit is to operate as an intermediate level decision node representing the associated pair of ways and a root level decision node having exactly two individual bits to point to one of the single bits to operate as the intermediate level decision nodes representing an associated pair of ways. In this exemplary embodiment, the total number of bits is N−1, wherein N is the total number of ways in the plurality of ways. Alternative structures are also presented for full LRU implementation, a “multiple of 5” number of cache ways, and variations of the “multiple of 3” number of cache ways.
摘要翻译：根据本文公开的实施例，提供了用于实现用于“3”倍的方式缓存的平衡P-LRU树的方法，系统，机制，技术和装置。例如，在一个实施例中，这种装置可以包括具有高速缓存和多个方式的集成电路。在这样的实施例中，多个方式包括量是三的倍数，而不是二的幂，并且其中多个方式被组织成多对。在这样的实施例中，装置还包括用于多个对中的每一对的单个位，其中每个单个位将用作表示相关联的方式的中间级决策节点，以及具有正好两个单独位的根级决策节点指向要作为表示相关联的方式的中间级决策节点操作的单个位之一。在该示例性实施例中，总数是N-1，其中N是多个方式的总路数。还提供了替代结构，用于完整的LRU实现，“多路复用5”缓存方式，以及“3”倍数缓存方式的变化。

7. 发明授权

US07930539B2 Computer system resource access control 有权
标题翻译：计算机系统资源访问控制
公开(公告)号：US07930539B2
公开(公告)日：2011-04-19
申请号：US10910652
申请日：2004-08-03
申请人： Donald C. Soltis, Jr. , Rohit Bhatia , Eric R. DeLano
发明人： Donald C. Soltis, Jr. , Rohit Bhatia , Eric R. DeLano
IPC分类号： H04L29/00 , G06F12/14 , G06F17/30
CPC分类号： G06F21/6281 , G06F2221/2105
摘要： In a computer system including a plurality of resources, a device receives a request from a software program to access a specified one of the plurality of resources, determines whether the specified one of the plurality of resources is a protected resource. If the specified one of the plurality of resources is a protected resource, the device denies the request if the computer system is operating in a protected mode of operation, and processes the request based on access rights associated with the software program if the computer system is not operating in the protected mode of operation.
摘要翻译：在包括多个资源的计算机系统中，设备接收来自软件程序的访问多个资源中指定的一个资源的请求，确定多个资源中指定的一个资源是否是受保护的资源。如果多个资源中的指定的资源是受保护的资源，则如果计算机系统在受保护的操作模式下操作，则设备拒绝该请求，并且如果计算机系统是不工作在受保护的操作模式。

8. 发明授权

US07634508B2 Processing of duplicate records having master/child relationship with other records 有权
标题翻译：处理与其他记录具有主/关关系的重复记录
公开(公告)号：US07634508B2
公开(公告)日：2009-12-15
申请号：US11729441
申请日：2007-03-29
申请人： Rohit Bhatia , Subodh Kumar , Nitin Mukhija , Abhishek Agarwal
发明人： Rohit Bhatia , Subodh Kumar , Nitin Mukhija , Abhishek Agarwal
IPC分类号： G06F17/00
CPC分类号： G06F17/30489
摘要： Duplicate record processing is enabled employing on customizable rules. Detected duplicate records are merged, deleted, deactivated, or moved based on one or more sets of customizable rules. Different rule sets may be used for each record type, or a rule set reused for different records. Hierarchical relationships between master and child records are adjusted upon duplicate processing based on rules and/or record attributes.
摘要翻译：启用了可定制规则的重复记录处理。根据一套或多套可自定义规则合并，删除，停用或移动检测到的重复记录。可以为每个记录类型使用不同的规则集，或者可以为不同的记录重用规则集。基于规则和/或记录属性的重复处理来调整主记录和子记录之间的分层关系。

9. 发明授权

US07421689B2 Processor-architecture for facilitating a virtual machine monitor 失效
标题翻译：处理器架构，便于虚拟机监控
公开(公告)号：US07421689B2
公开(公告)日：2008-09-02
申请号：US10695267
申请日：2003-10-28
申请人： Jonathan K. Ross , Dale Morris , Donald C. Soltis, Jr. , Rohit Bhatia , Eric Delano
发明人： Jonathan K. Ross , Dale Morris , Donald C. Soltis, Jr. , Rohit Bhatia , Eric Delano
IPC分类号： G06F9/455
CPC分类号： G06F9/45533
摘要： Virtual-machine-monitor operation and implementation is facilitated by number of easily implemented features and extensions added to the features of a processor architecture. These features, one or more of which are used in various embodiments of the present invention, include a vmsw instruction that provides a means for transitioning between virtualization mode and non-virtualization mode without an interruption, a virtualization fault that faults on an attempt by a priority-0 routine in virtualization mode attempting to execute a privileged instruction, and a flexible highest-implemented-address mechanism to partition virtual address space into a virtualization address space and a non-virtualization address space.
摘要翻译：虚拟机监视器的操作和实现通过添加到处理器架构的特征中的容易实现的特征和扩展的数量来实现。这些特征，其中一个或多个在本发明的各种实施例中使用，包括提供用于在不中断的情况下在虚拟化模式和非虚拟化模式之间转换的手段的vmsw指令，虚拟化故障，尝试执行特权指令的虚拟化模式中的优先级0例程，以及将虚拟地址空间划分为虚拟化地址空间和非虚拟化地址空间的灵活的最高实现地址机制。

10. 发明授权

US07409524B2 System and method for responding to TLB misses 失效
标题翻译：用于响应TLB未命中的系统和方法
公开(公告)号：US07409524B2
公开(公告)日：2008-08-05
申请号：US11205622
申请日：2005-08-17
申请人： Kevin Safford , Rohit Bhatia , Karl Brummel
发明人： Kevin Safford , Rohit Bhatia , Karl Brummel
IPC分类号： G06F12/00
CPC分类号： G06F12/1063 , G06F12/1018
摘要： The present invention relates to an improved microprocessor having a memory system with several caches that can be operated to provide virtual memory. Among the caches included in the microprocessor are conventional caches that store data and instructions to be utilized by the processes being performed by the microprocessor, and that are typically arranged in a cache hierarchy, as well as one or more translation lookaside buffer (TLB) caches that store a limited number of virtual page translations. The improved microprocessor also has an additional cache that serves to store a virtual hash page table (VHPT) that is accessed when TLB misses occur. The introduction of this VHPT cache eliminates or at least reduces the need for the microprocessor to look for information within the caches of the cache hierarchy or in other memory (e.g., main memory) outside of the microprocessor when TLB misses occur, and consequently enhances microprocessor speed.
摘要翻译：本发明涉及一种改进的微处理器，具有具有多个可以操作以提供虚拟存储器的高速缓存的存储器系统。在微处理器中包括的高速缓冲存储器中的是传统的高速缓冲存储器，其存储由微处理器执行的处理使用的数据和指令，并且通常被布置在高速缓存层级中，以及一个或多个转换后备缓冲器（TLB）高速缓存它存储有限数量的虚拟页面翻译。改进的微处理器还具有额外的高速缓存，用于存储当TLB未命中时被访问的虚拟散列页表（VHPT）。这种VHPT高速缓存的引入消除或至少减少了在发生TLB缺失时微处理器在高速缓存层级或高速缓存之外的其他存储器（例如，主存储器）中寻找信息的需要，从而增强了微处理器速度。

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