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1. 发明申请

US20140173207A1 Power Gating A Portion Of A Cache Memory 有权
标题翻译：电源门控部分缓存内存
公开(公告)号：US20140173207A1
公开(公告)日：2014-06-19
申请号：US13715613
申请日：2012-12-14
申请人： Ren Wang , Ahmad Samih , Eric Delano , Pinkesh J. Shah , Zeshan A. Chishti , Christian Maciocco , Tsung-Yuan Charlie Tai
发明人： Ren Wang , Ahmad Samih , Eric Delano , Pinkesh J. Shah , Zeshan A. Chishti , Christian Maciocco , Tsung-Yuan Charlie Tai
IPC分类号： G06F12/08
CPC分类号： G06F12/0802 , G06F1/32 , G06F1/3215 , G06F1/3225 , G06F1/3243 , G06F1/3287 , G06F12/0811 , G06F2212/1028 , Y02D10/13
摘要： In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括多个瓦片，每个瓦片包括核心和瓦片高速缓存层级。该瓦片高速缓存层级包括第一级高速缓存，中级缓存（MLC）和最后级高速缓存（LLC），并且这些高速缓存中的每一个对于该瓦片是私有的。耦合到瓦片的控制器包括高速缓存功率控制逻辑，用于至少部分地基于该信息来接收关于瓦片的核心和瓦片高速缓存层级的利用信息，并且使瓦片的LLC独立地进行电源门控。描述和要求保护其他实施例。

2. 发明申请

US20050240811A1 Core-level processor lockstepping 有权
标题翻译：核心级处理器锁步
公开(公告)号：US20050240811A1
公开(公告)日：2005-10-27
申请号：US10818975
申请日：2004-04-06
申请人： Kevin Safford , Christopher Lyles , Eric Delano
发明人： Kevin Safford , Christopher Lyles , Eric Delano
IPC分类号： G06F11/18 , G06F11/00 , G06F11/16 , G06F11/20
CPC分类号： G06F11/1679 , G06F11/1641
摘要： A device is provided which includes a first microprocessor core to generate a first output signal; a second microprocessor core to generate a second output signal; a switching fabric having a first input/output port; and lockstep logic, coupled between the first input/output port of the switching fabric and the first and second microprocessor cores, to detect whether the first output signal differs from the second output signal.
摘要翻译：提供一种装置，其包括用于产生第一输出信号的第一微处理器核心; 第二微处理器核心，用于产生第二输出信号; 具有第一输入/输出端口的交换结构; 以及耦合在交换结构的第一输入/输出端口与第一和第二微处理器核心之间的锁步逻辑，以检测第一输出信号是否与第二输出信号不同。

3. 发明申请

US20050138478A1 Error detection method and system for processors that employ alternating threads 审中-公开
标题翻译：使用交替线程的处理器的错误检测方法和系统
公开(公告)号：US20050138478A1
公开(公告)日：2005-06-23
申请号：US10714258
申请日：2003-11-14
申请人： Kevin Safford , Donald Soltis , Stephen Undy , James Gibson , Eric Delano
发明人： Kevin Safford , Donald Soltis , Stephen Undy , James Gibson , Eric Delano
IPC分类号： G06F11/14 , G06F11/00
CPC分类号： G06F11/1497 , G06F9/3861
摘要： Microprocessor that includes a mechanism for detecting soft errors. The processor includes an instruction fetch unit for fetching an instruction and an instruction decoder for decoding the instruction. The mechanism for detecting soft errors includes duplication hardware for duplicating the instruction and comparison hardware. The processor further includes a first execution unit for executing the instruction in a first execution cycle and the duplicated instruction in a second execution cycle. The comparison hardware compares the results of the first execution cycle and the results of the second execution cycle. The comparison hardware can include an exception unit for generating an exception (e.g., raising a fault) when the results are not the same. The processor also includes a commit unit for committing one of the results when the results are the same.
摘要翻译：微处理器，包括检测软错误的机制。处理器包括用于取出指令的指令获取单元和用于解码指令的指令解码器。用于检测软错误的机制包括用于复制指令和比较硬件的复制硬件。处理器还包括用于在第一执行周期中执行指令的第一执行单元和在第二执行周期中的复制指令。比较硬件比较第一个执行周期的结果和第二个执行周期的结果。当结果不相同时，比较硬件可以包括用于产生异常（例如，引起故障）的异常单元。处理器还包括提交单元，用于在结果相同时提交其中一个结果。

4. 发明申请

US20110078492A1 HOME AGENT DATA AND MEMORY MANAGEMENT 失效
标题翻译：家庭代理数据和内存管理
公开(公告)号：US20110078492A1
公开(公告)日：2011-03-31
申请号：US12571381
申请日：2009-09-30
申请人： Ganesh Kumar , Dheemanth Nagaraj , Vincent R. Freytag , Eric Delano , Gregory S. Averill
发明人： Ganesh Kumar , Dheemanth Nagaraj , Vincent R. Freytag , Eric Delano , Gregory S. Averill
IPC分类号： G06F11/00 , G06F12/08 , G06F12/00
CPC分类号： G06F12/0817
摘要： Methods and apparatus relating to home agent data and memory management are described. In one embodiment, a scrubber logic corrects an error at a location in a memory corresponding to a target address by writing back the corrected version of data to the target location. In an embodiment, a map out logic maps out an index or way of a directory cache in response to a number of errors, corresponding to the directory cache, exceeding a threshold value. Other embodiments are also disclosed.
摘要翻译：描述与归属代理数据和存储器管理有关的方法和装置。在一个实施例中，洗涤器逻辑通过将校正的数据版本写回到目标位置来校正与目标地址相对应的存储器中的位置处的错误。在一个实施例中，映射逻辑响应于对应于目录高速缓存的多个错误超过阈值来映射目录高速缓存的索引或方式。还公开了其他实施例。

5. 发明授权

US07734741B2 Method, system, and apparatus for dynamic reconfiguration of resources 有权
标题翻译：用于动态重新配置资源的方法，系统和装置
公开(公告)号：US07734741B2
公开(公告)日：2010-06-08
申请号：US11011300
申请日：2004-12-13
申请人： Mani Ayyar , Eric Delano , Ioannis T. Schoinas , Akhilesh Kumar , Jay Jayasimha , Jose A. Vargas
发明人： Mani Ayyar , Eric Delano , Ioannis T. Schoinas , Akhilesh Kumar , Jay Jayasimha , Jose A. Vargas
IPC分类号： G06F15/177
CPC分类号： G06F9/44505 , G06F9/50 , G06F9/5011 , G06F13/00 , G06F13/24 , G06F13/4081 , G06F13/409
摘要： A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.
摘要翻译：动态重新配置，包括单独模块的在线添加，删除和替换，以支持系统的动态分区，互连（链接）重新配置，存储器RAS以允许无OS干预的迁移和镜像，动态内存重新交织，CPU和插座描述了跨分区的全局共享内存的迁移和支持。为了便于在线添加或删除，固件能够静默和解除感兴趣的域，以便许多系统资源（如路由表和地址解码器）可以在基本上看起来是原子操作到固件上方的软件层。

6. 发明申请

US20090055600A1 Method, System, and Apparatus for Dynamic Reconfiguration of Resources 审中-公开
标题翻译：用于资源动态重新配置的方法，系统和装置
公开(公告)号：US20090055600A1
公开(公告)日：2009-02-26
申请号：US12236222
申请日：2008-09-23
申请人： Mani Ayyar , Eric Delano , Ioannis T. Schoinas , Akhiles Kumar , Jay Jayasimha , Jose A. Vargas
发明人： Mani Ayyar , Eric Delano , Ioannis T. Schoinas , Akhiles Kumar , Jay Jayasimha , Jose A. Vargas
IPC分类号： G06F12/00
CPC分类号： G06F9/44505 , G06F9/50 , G06F9/5011 , G06F13/00 , G06F13/24 , G06F13/4081 , G06F13/409
摘要： A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.
摘要翻译：动态重新配置，包括单独模块的在线添加，删除和替换，以支持系统的动态分区，互连（链接）重新配置，存储器RAS以允许无OS干预的迁移和镜像，动态内存重新交织，CPU和插座描述了跨分区的全局共享内存的迁移和支持。为了便于在线添加或删除，固件能够静默和解除感兴趣的域，以便许多系统资源（如路由表和地址解码器）可以在基本上看起来是原子操作到固件上方的软件层。

7. 发明授权

US07421689B2 Processor-architecture for facilitating a virtual machine monitor 失效
标题翻译：处理器架构，便于虚拟机监控
公开(公告)号：US07421689B2
公开(公告)日：2008-09-02
申请号：US10695267
申请日：2003-10-28
申请人： Jonathan K. Ross , Dale Morris , Donald C. Soltis, Jr. , Rohit Bhatia , Eric Delano
发明人： Jonathan K. Ross , Dale Morris , Donald C. Soltis, Jr. , Rohit Bhatia , Eric Delano
IPC分类号： G06F9/455
CPC分类号： G06F9/45533
摘要： Virtual-machine-monitor operation and implementation is facilitated by number of easily implemented features and extensions added to the features of a processor architecture. These features, one or more of which are used in various embodiments of the present invention, include a vmsw instruction that provides a means for transitioning between virtualization mode and non-virtualization mode without an interruption, a virtualization fault that faults on an attempt by a priority-0 routine in virtualization mode attempting to execute a privileged instruction, and a flexible highest-implemented-address mechanism to partition virtual address space into a virtualization address space and a non-virtualization address space.
摘要翻译：虚拟机监视器的操作和实现通过添加到处理器架构的特征中的容易实现的特征和扩展的数量来实现。这些特征，其中一个或多个在本发明的各种实施例中使用，包括提供用于在不中断的情况下在虚拟化模式和非虚拟化模式之间转换的手段的vmsw指令，虚拟化故障，尝试执行特权指令的虚拟化模式中的优先级0例程，以及将虚拟地址空间划分为虚拟化地址空间和非虚拟化地址空间的灵活的最高实现地址机制。

8. 发明授权

US07310751B2 Timeout event trigger generation 有权
标题翻译：超时事件触发器生成
公开(公告)号：US07310751B2
公开(公告)日：2007-12-18
申请号：US10783112
申请日：2004-02-20
申请人： Michael Tayler , Eric Delano
发明人： Michael Tayler , Eric Delano
IPC分类号： G06F11/00
CPC分类号： G06F11/076
摘要： A system is disclosed for generating a plurality of timeout event triggers in response to a plurality of kinds of timeout events. The system includes an overflow generator, which generates a plurality of overflow signals having a plurality of periods. The system also includes a plurality of trigger generators corresponding to the plurality of kinds of timeout events. Each of the plurality of trigger generators is associated with a corresponding timeout threshold value representing the minimum amount of time that must elapse for the trigger generator to generate a timeout event trigger. For each of the plurality of timeout triggers, a corresponding selection signal selects one of the plurality of periodic overflow signals. The timeout threshold corresponding to each timeout trigger is equal to the period of the corresponding selected overflow signal multiplied by the value of the corresponding control signal.
摘要翻译：公开了用于响应于多种超时事件而产生多个超时事件触发的系统。该系统包括溢出发生器，其产生具有多个周期的多个溢出信号。该系统还包括与多种超时事件对应的多个触发发生器。多个触发发生器中的每一个与相应的超时阈值相关联，该阈值表示触发器产生器必须经过的生成超时事件触发的最小时间量。对于多个超时触发中的每一个，相应的选择信号选择多个周期性溢出信号中的一个。对应于每个超时触发的超时阈值等于对应的所选溢出信号乘以相应控制信号的值的周期。

9. 发明申请

US20070150699A1 Firm partitioning in a system with a point-to-point interconnect 审中-公开
标题翻译：在具有点对点互连的系统中进行牢固的分区
公开(公告)号：US20070150699A1
公开(公告)日：2007-06-28
申请号：US11321213
申请日：2005-12-28
申请人： Ioannis Schoinas , Doddaballapur Jayasimha , Eric Delano , Allen Baum , Akhilesh Kumar , Steven Chang , Suresh Chittor , Kenneth Creta , Stephen Van Doren
发明人： Ioannis Schoinas , Doddaballapur Jayasimha , Eric Delano , Allen Baum , Akhilesh Kumar , Steven Chang , Suresh Chittor , Kenneth Creta , Stephen Van Doren
IPC分类号： G06F15/00
CPC分类号： H04L45/00 , H04L45/04
摘要： Methods and apparatuses for firm partitioning of a computing platform.
摘要翻译：用于计算平台的固定分区的方法和装置。

10. 发明申请

US20060184480A1 Method, system, and apparatus for dynamic reconfiguration of resources 有权
公开(公告)号：US20060184480A1
公开(公告)日：2006-08-17
申请号：US11011300
申请日：2004-12-13
申请人： Mani Ayyar , Eric Delano , Ioannis Schoinas , Akhilesh Kumar , Jay Jayasimha , Jose Vargas
发明人： Mani Ayyar , Eric Delano , Ioannis Schoinas , Akhilesh Kumar , Jay Jayasimha , Jose Vargas
IPC分类号： G06N5/00
CPC分类号： G06F9/44505 , G06F9/50 , G06F9/5011 , G06F13/00 , G06F13/24 , G06F13/4081 , G06F13/409
摘要： A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.

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