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1. 发明授权

US09159732B2 Semiconductor device with buried gate and method for fabricating the same 有权
标题翻译：具有埋栅的半导体器件及其制造方法
公开(公告)号：US09159732B2
公开(公告)日：2015-10-13
申请号：US13553307
申请日：2012-07-19
申请人： Jong-Han Shin , Jum-Yong Park
发明人： Jong-Han Shin , Jum-Yong Park
IPC分类号： H01L29/66 , H01L27/108 , H01L29/423
CPC分类号： H01L27/10876 , H01L27/10855 , H01L27/10888 , H01L29/4236
摘要： A method for fabricating a semiconductor device includes forming landing plugs over a substrate, forming a trench by etching the substrate between the landing plugs, forming a buried gate to partially fill the trench, forming a gap-fill layer to gap-fill an upper side of the buried gate, forming protruding portions of the landing plugs, and trimming the protruding portions of the landing plugs.
摘要翻译：一种用于制造半导体器件的方法包括在衬底上形成覆盖层，通过在层间塞之间蚀刻衬底形成沟槽，形成掩埋栅极以部分填充沟槽，形成间隙填充层以间隙填充上侧，形成所述着陆塞的突出部分，以及修剪所述着陆塞的突出部分。

2. 发明申请

US20110156262A1 SEMICONDUCTOR DEVICE WITH BURIED GATE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：具有开口门的半导体器件及其制造方法
公开(公告)号：US20110156262A1
公开(公告)日：2011-06-30
申请号：US12827385
申请日：2010-06-30
申请人： Jong-Han Shin , Jum-Yong Park
发明人： Jong-Han Shin , Jum-Yong Park
IPC分类号： H01L29/41 , H01L21/28
CPC分类号： H01L27/10876 , H01L27/10855 , H01L27/10888 , H01L29/4236
摘要： A method for fabricating a semiconductor device includes forming landing plugs over a substrate, forming a trench by etching the substrate between the landing plugs, forming a buried gate to partially fill the trench, forming a gap-fill layer to gap-fill an upper side of the buried gate, forming protruding portions of the landing plugs, and trimming the protruding portions of the landing plugs.
摘要翻译：一种用于制造半导体器件的方法包括在衬底上形成覆盖层，通过在层间塞之间蚀刻衬底形成沟槽，形成掩埋栅极以部分填充沟槽，形成间隙填充层以间隙填充上侧，形成所述着陆塞的突出部分，以及修剪所述着陆塞的突出部分。

3. 发明申请

US20090117739A1 METHOD FOR FORMING PATTERN IN SEMICONDUCTOR DEVICE 失效
标题翻译：在半导体器件中形成图案的方法
公开(公告)号：US20090117739A1
公开(公告)日：2009-05-07
申请号：US11965582
申请日：2007-12-27
申请人： Jong-Han Shin , Hyung-Soon Park , Cheol-Hwi Ryu , Jum-Yong Park , Sung-Jun Kim
发明人： Jong-Han Shin , Hyung-Soon Park , Cheol-Hwi Ryu , Jum-Yong Park , Sung-Jun Kim
IPC分类号： H01L21/306
CPC分类号： H01L21/0337 , H01L21/0334 , H01L27/105 , H01L27/1052 , H01L27/10894
摘要： A method for forming a pattern in a semiconductor device includes forming an etch-target layer over a substrate, wherein the substrate includes a first region having a smaller pattern than the first region, forming a sacrificial layer and a passivation layer over the etch-target layer, etching the passivation layer and the sacrificial layer to form stack structures including a sacrificial pattern and a passivation pattern, forming spacers over sidewalls of the stack structures, forming a mask pattern covering the second region, removing a portion of the passivation pattern in the first region exposed by the mask pattern to expose a portion of the sacrificial pattern in the first region, removing the exposed portion of the sacrificial pattern in the first region, and etching the etch-target layer to form an etch-target pattern using the spacers in the first and second regions and the stack structure formed between the spacers in the second region.
摘要翻译：在半导体器件中形成图案的方法包括在衬底上形成蚀刻目标层，其中衬底包括具有比第一区域更小的图案的第一区域，在蚀刻靶上形成牺牲层和钝化层蚀刻钝化层和牺牲层以形成包括牺牲图案和钝化图案的堆叠结构，在堆叠结构的侧壁上形成间隔物，形成覆盖第二区域的掩模图案，从而去除钝化层的一部分第一区域由掩模图案曝光以暴露第一区域中的牺牲图案的一部分，去除第一区域中的牺牲图案的暴露部分，以及蚀刻蚀刻目标层，以使用间隔物在第一区域和第二区域中形成叠层结构，并且在第二区域中形成在间隔物之间。

4. 发明授权

US07994056B2 Method for forming pattern in semiconductor device 失效
标题翻译：在半导体器件中形成图案的方法
公开(公告)号：US07994056B2
公开(公告)日：2011-08-09
申请号：US11965582
申请日：2007-12-27
申请人： Jong-Han Shin , Hyung-Soon Park , Cheol-Hwi Ryu , Jum-Yong Park , Sung-Jun Kim
发明人： Jong-Han Shin , Hyung-Soon Park , Cheol-Hwi Ryu , Jum-Yong Park , Sung-Jun Kim
IPC分类号： H01L21/301 , H01L21/461 , H01L21/311 , C03C15/00 , C03C25/68 , C23F1/00
CPC分类号： H01L21/0337 , H01L21/0334 , H01L27/105 , H01L27/1052 , H01L27/10894
摘要： A method for forming a pattern in a semiconductor device includes forming an etch-target layer over a substrate, wherein the substrate includes a first region having a smaller pattern than the first region, forming a sacrificial layer and a passivation layer over the etch-target layer, etching the passivation layer and the sacrificial layer to form stack structures including a sacrificial pattern and a passivation pattern, forming spacers over sidewalls of the stack structures, forming a mask pattern covering the second region, removing a portion of the passivation pattern in the first region exposed by the mask pattern to expose a portion of the sacrificial pattern in the first region, removing the exposed portion of the sacrificial pattern in the first region, and etching the etch-target layer to form an etch-target pattern using the spacers in the first and second regions and the stack structure formed between the spacers in the second region.
摘要翻译：在半导体器件中形成图案的方法包括在衬底上形成蚀刻目标层，其中衬底包括具有比第一区域更小的图案的第一区域，在蚀刻靶上形成牺牲层和钝化层蚀刻钝化层和牺牲层以形成包括牺牲图案和钝化图案的堆叠结构，在堆叠结构的侧壁上形成间隔物，形成覆盖第二区域的掩模图案，从而去除钝化层中的钝化图案的一部分第一区域由掩模图案曝光以暴露第一区域中的牺牲图案的一部分，去除第一区域中的牺牲图案的暴露部分，以及蚀刻蚀刻目标层，以使用间隔物在第一区域和第二区域中形成叠层结构，并且在第二区域中形成在间隔物之间。

5. 发明授权

US08357600B2 Method for fabricating buried gate using pre landing plugs 有权
标题翻译：使用预先着陆插头制造埋栅的方法
公开(公告)号：US08357600B2
公开(公告)日：2013-01-22
申请号：US12613708
申请日：2009-11-06
申请人： Jong-Han Shin , Jum-Yong Park
发明人： Jong-Han Shin , Jum-Yong Park
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/8242
CPC分类号： H01L21/28017 , H01L27/105 , H01L27/10823 , H01L27/10876 , H01L27/10894 , H01L27/10897 , H01L29/4236
摘要： A method for fabricating a semiconductor device is provided, the method includes forming a plug conductive layer over an entire surface of a substrate, etching the plug conductive layer to form landing plugs, etching the substrate between the landing plugs to form a trench, forming a gate insulation layer over a surface of the trench and forming a buried gate partially filling the trench over the gate insulation layer.
摘要翻译：提供一种制造半导体器件的方法，该方法包括在衬底的整个表面上形成插头导电层，蚀刻插头导电层以形成着陆塞，蚀刻层压塞之间的衬底以形成沟槽，形成栅极绝缘层，并且形成在门绝缘层上部分地填充沟槽的掩埋栅极。

6. 发明授权

US08247324B2 Semiconductor device with buried gate and method for fabricating the same 有权
标题翻译：具有埋栅的半导体器件及其制造方法
公开(公告)号：US08247324B2
公开(公告)日：2012-08-21
申请号：US12827385
申请日：2010-06-30
申请人： Jong-Han Shin , Jum-Yong Park
发明人： Jong-Han Shin , Jum-Yong Park
IPC分类号： H01L21/44
CPC分类号： H01L27/10876 , H01L27/10855 , H01L27/10888 , H01L29/4236
摘要： A method for fabricating a semiconductor device includes forming landing plugs over a substrate, forming a trench by etching the substrate between the landing plugs, forming a buried gate to partially fill the trench, forming a gap-fill layer to gap-fill an upper side of the buried gate, forming protruding portions of the landing plugs, and trimming the protruding portions of the landing plugs.
摘要翻译：一种用于制造半导体器件的方法包括在衬底上形成覆盖层，通过在层间塞之间蚀刻衬底形成沟槽，形成掩埋栅极以部分填充沟槽，形成间隙填充层以间隙填充上侧，形成所述着陆塞的突出部分，以及修剪所述着陆塞的突出部分。

7. 发明授权

US07981797B2 Phase-change random access memory device and method of manufacturing the same 有权
标题翻译：相变随机存取存储器件及其制造方法
公开(公告)号：US07981797B2
公开(公告)日：2011-07-19
申请号：US12146179
申请日：2008-06-25
申请人： Cheol-Hwi Ryu , Hyung-Soon Park , Jong-Han Shin , Jum-Yong Park , Sung-Jun Kim
发明人： Cheol-Hwi Ryu , Hyung-Soon Park , Jong-Han Shin , Jum-Yong Park , Sung-Jun Kim
IPC分类号： H01L21/44
CPC分类号： H01L27/101 , H01L45/06 , H01L45/124 , H01L45/1683
摘要： A method of manufacturing a phase-change random access memory device includes forming an interlayer insulating film on a semiconductor substrate, on which a bottom structure is formed, and patterning the interlayer insulating film to form a contact hole, forming a spacer on the side wall of the contact hole; forming a dielectric layer in the contact hole, and removing the spacer to form a bottom electrode contact hole. Therefore, the contact area between the bottom electrode contact and the phase-change material layer can be minimized.
摘要翻译：一种制造相变随机存取存储器件的方法包括在半导体衬底上形成层间绝缘膜，在其上形成底部结构，并对该层间绝缘膜进行构图以形成接触孔，在侧壁上形成间隔物的接触孔; 在接触孔中形成电介质层，并且去除间隔物以形成底部电极接触孔。因此，可以使底部电极接触和相变材料层之间的接触面积最小化。

8. 发明申请

US20110003459A1 METHOD FOR FABRICATING BURIED GATE USING PRE LANDING PLUGS 有权
标题翻译：使用预制线制造布盖板的方法
公开(公告)号：US20110003459A1
公开(公告)日：2011-01-06
申请号：US12613708
申请日：2009-11-06
申请人： Jong-Han Shin , Jum-Yong Park
发明人： Jong-Han Shin , Jum-Yong Park
IPC分类号： H01L21/28 , H01L21/762
CPC分类号： H01L21/28017 , H01L27/105 , H01L27/10823 , H01L27/10876 , H01L27/10894 , H01L27/10897 , H01L29/4236
摘要： A method for fabricating a semiconductor device is provided, the method includes forming a plug conductive layer over an entire surface of a substrate, etching the plug conductive layer to form landing plugs, etching the substrate between the landing plugs to form a trench, forming a gate insulation layer over a surface of the trench and forming a buried gate partially filling the trench over the gate insulation layer.
摘要翻译：提供一种制造半导体器件的方法，该方法包括在衬底的整个表面上形成插头导电层，蚀刻插头导电层以形成着陆塞，蚀刻层压塞之间的衬底以形成沟槽，形成栅极绝缘层，并且形成在门绝缘层上部分地填充沟槽的掩埋栅极。

9. 发明申请

US20090124082A1 SLURRY FOR POLISHING RUTHENIUM AND METHOD FOR POLISHING USING THE SAME 审中-公开
标题翻译：用于抛光的浆料和使用其抛光的方法
公开(公告)号：US20090124082A1
公开(公告)日：2009-05-14
申请号：US12165252
申请日：2008-06-30
申请人： Hyung-Soon PARK , Jin-Woong Kim , Noh-Jung Kwak , Yong-Soo Choi , Jong-Han Shin , Cheol-Hwi Ruy , Jum-Yong Park , Sung-Jun Kim , Jin-Goo Park , In-Kwon Kim , Tae-Young Kwon
发明人： Hyung-Soon PARK , Jin-Woong Kim , Noh-Jung Kwak , Yong-Soo Choi , Jong-Han Shin , Cheol-Hwi Ruy , Jum-Yong Park , Sung-Jun Kim , Jin-Goo Park , In-Kwon Kim , Tae-Young Kwon
IPC分类号： H01L21/304 , C09K3/14
CPC分类号： C09G1/02 , H01L21/3212
摘要： A slurry for polishing a ruthenium layer comprises distilled water, sodium periodate (NaIO4), an abrasive and a pH controlling agent.
摘要翻译：用于抛光钌层的浆料包括蒸馏水，高碘酸钠（NaIO 4），研磨剂和pH控制剂。

10. 发明申请

US20100184359A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20100184359A1
公开(公告)日：2010-07-22
申请号：US12489747
申请日：2009-06-23
申请人： Jum-Yong Park , Noh-Jung Kwak , Yong-Soo Choi , Cheol-Hwi Ryu
发明人： Jum-Yong Park , Noh-Jung Kwak , Yong-Soo Choi , Cheol-Hwi Ryu
IPC分类号： B24B37/04 , B24B1/00
CPC分类号： C09G1/02 , B24B37/044
摘要： A method for fabricating a semiconductor device through a chemical mechanical polishing (CMP) process is provided. The CMP process is performed by using a slurry. The semiconductor device fabrication method can ensure the reliability and economical efficiency of the device by performing a CMP process using a CMP slurry having a high polishing selectivity with respect to a target surface, an anti-scratch characteristic, and a high global planarization characteristic.
摘要翻译：提供了一种通过化学机械抛光（CMP）工艺制造半导体器件的方法。 CMP工艺通过使用浆料进行。半导体器件制造方法可以通过使用相对于目标表面具有高抛光选择性的CMP浆料，抗划痕特性和高全局平坦化特性进行CMP工艺来确保器件的可靠性和经济效率。

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