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1. 发明授权

US09257436B2 Semiconductor device with buried gates and fabrication method thereof 有权
标题翻译：具有埋栅的半导体器件及其制造方法
公开(公告)号：US09257436B2
公开(公告)日：2016-02-09
申请号：US13325552
申请日：2011-12-14
申请人： Jong-Han Shin
发明人： Jong-Han Shin
IPC分类号： H01L21/336 , H01L27/108 , H01L29/423
CPC分类号： H01L29/4236 , H01L27/1052 , H01L27/10873 , H01L27/10876 , H01L27/10888 , H01L27/10894 , H01L29/42352 , H01L29/42356
摘要： A semiconductor device includes a substrate having a cell region and a peripheral region, a buried gate formed over the substrate of the cell region, a peripheral gate formed over the substrate of the peripheral region and comprising a conductive layer, an inter-layer dielectric layer that covers the substrate, and a peripheral bit line formed inside the inter-layer dielectric layer and contacting the conductive layer.
摘要翻译：半导体器件包括具有单元区域和外围区域的衬底，形成在单元区域的衬底上的掩埋栅极，形成在周边区域的衬底上的外围栅极，并且包括导电层，层间电介质层覆盖衬底以及形成在层间电介质层内部并与导电层接触的外围位线。

2. 发明申请

US20110159664A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH BURIED GATES 有权
标题翻译：用于制造具有开口盖的半导体器件的方法
公开(公告)号：US20110159664A1
公开(公告)日：2011-06-30
申请号：US12832137
申请日：2010-07-08
申请人： Jong-Han SHIN , Noh-Jung Kwak , Myung-Ok Kim
发明人： Jong-Han SHIN , Noh-Jung Kwak , Myung-Ok Kim
IPC分类号： H01L21/76 , H01L21/768
CPC分类号： H01L21/76229 , H01L21/76897 , H01L27/10876 , H01L27/10894 , H01L29/4236 , H01L29/66621
摘要： A method for fabricating a semiconductor device includes sequentially stacking a pad oxide layer and a hard mask layer over a substrate, forming a device isolation layer over the substrate, forming a capping layer pattern configured to open a first region of the substrate and cover a second region of the substrate, removing the hard mask layer, removing the capping layer pattern, and removing the pad oxide layer.
摘要翻译：一种用于制造半导体器件的方法包括在衬底上顺序堆叠衬垫氧化物层和硬掩模层，在衬底上形成器件隔离层，形成覆盖衬底图案，其构造成打开衬底的第一区域并覆盖第二区域，去除硬掩模层，去除覆盖层图案，以及去除焊盘氧化物层。

3. 发明申请

US20110156262A1 SEMICONDUCTOR DEVICE WITH BURIED GATE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：具有开口门的半导体器件及其制造方法
公开(公告)号：US20110156262A1
公开(公告)日：2011-06-30
申请号：US12827385
申请日：2010-06-30
申请人： Jong-Han Shin , Jum-Yong Park
发明人： Jong-Han Shin , Jum-Yong Park
IPC分类号： H01L29/41 , H01L21/28
CPC分类号： H01L27/10876 , H01L27/10855 , H01L27/10888 , H01L29/4236
摘要： A method for fabricating a semiconductor device includes forming landing plugs over a substrate, forming a trench by etching the substrate between the landing plugs, forming a buried gate to partially fill the trench, forming a gap-fill layer to gap-fill an upper side of the buried gate, forming protruding portions of the landing plugs, and trimming the protruding portions of the landing plugs.
摘要翻译：一种用于制造半导体器件的方法包括在衬底上形成覆盖层，通过在层间塞之间蚀刻衬底形成沟槽，形成掩埋栅极以部分填充沟槽，形成间隙填充层以间隙填充上侧，形成所述着陆塞的突出部分，以及修剪所述着陆塞的突出部分。

4. 发明授权

US07871913B2 Method for manufacturing semiconductor device having vertical transistor 有权
标题翻译：具有垂直晶体管的半导体器件的制造方法
公开(公告)号：US07871913B2
公开(公告)日：2011-01-18
申请号：US12335668
申请日：2008-12-16
申请人： Jong Han Shin , Hyung Soon Park , Jum Yong Park , Sung Jun Kim
发明人： Jong Han Shin , Hyung Soon Park , Jum Yong Park , Sung Jun Kim
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L29/66666 , H01L29/4236 , H01L29/42376 , H01L29/7827
摘要： A method for manufacturing a semiconductor device having a vertical transistor includes forming hard masks on a semiconductor substrate to expose portions of the semiconductor substrate. Then the exposed portions of the semiconductor substrate are etched to define grooves in the semiconductor substrate. A gate conductive layer is formed on the hard masks and surfaces of the grooves to a thickness that does not completely fill the grooves. A sacrificial layer is formed on the gate conductive layer to completely fill the grooves. A partial thickness of the sacrificial layer is removed to expose the gate conductive layer and portions of the gate conductive layer formed on the hard masks and on sidewalls of upper portions of the grooves are removed. The remaining sacrificial layer is completely removed. Gates are formed on sidewalls of lower portions of the grooves by etching the gate conductive layer.
摘要翻译：一种制造具有垂直晶体管的半导体器件的方法包括：在半导体衬底上形成硬掩模以暴露半导体衬底的部分。然后蚀刻半导体衬底的暴露部分以在半导体衬底中限定凹槽。在硬掩模和凹槽的表面上形成栅极导电层至不完全填充凹槽的厚度。牺牲层形成在栅极导电层上以完全填充凹槽。去除牺牲层的部分厚度以露出栅极导电层，并且去除形成在硬掩模上的栅极导电层的部分以及沟槽上部的侧壁上的部分。剩余的牺牲层被完全去除。通过蚀刻栅极导电层在栅极的下部的侧壁上形成栅极。

5. 发明申请

US20090117739A1 METHOD FOR FORMING PATTERN IN SEMICONDUCTOR DEVICE 失效
标题翻译：在半导体器件中形成图案的方法
公开(公告)号：US20090117739A1
公开(公告)日：2009-05-07
申请号：US11965582
申请日：2007-12-27
申请人： Jong-Han Shin , Hyung-Soon Park , Cheol-Hwi Ryu , Jum-Yong Park , Sung-Jun Kim
发明人： Jong-Han Shin , Hyung-Soon Park , Cheol-Hwi Ryu , Jum-Yong Park , Sung-Jun Kim
IPC分类号： H01L21/306
CPC分类号： H01L21/0337 , H01L21/0334 , H01L27/105 , H01L27/1052 , H01L27/10894
摘要： A method for forming a pattern in a semiconductor device includes forming an etch-target layer over a substrate, wherein the substrate includes a first region having a smaller pattern than the first region, forming a sacrificial layer and a passivation layer over the etch-target layer, etching the passivation layer and the sacrificial layer to form stack structures including a sacrificial pattern and a passivation pattern, forming spacers over sidewalls of the stack structures, forming a mask pattern covering the second region, removing a portion of the passivation pattern in the first region exposed by the mask pattern to expose a portion of the sacrificial pattern in the first region, removing the exposed portion of the sacrificial pattern in the first region, and etching the etch-target layer to form an etch-target pattern using the spacers in the first and second regions and the stack structure formed between the spacers in the second region.
摘要翻译：在半导体器件中形成图案的方法包括在衬底上形成蚀刻目标层，其中衬底包括具有比第一区域更小的图案的第一区域，在蚀刻靶上形成牺牲层和钝化层蚀刻钝化层和牺牲层以形成包括牺牲图案和钝化图案的堆叠结构，在堆叠结构的侧壁上形成间隔物，形成覆盖第二区域的掩模图案，从而去除钝化层的一部分第一区域由掩模图案曝光以暴露第一区域中的牺牲图案的一部分，去除第一区域中的牺牲图案的暴露部分，以及蚀刻蚀刻目标层，以使用间隔物在第一区域和第二区域中形成叠层结构，并且在第二区域中形成在间隔物之间。

6. 发明授权

US08623727B2 Method for fabricating semiconductor device with buried gate 失效
标题翻译：具有埋栅的半导体器件的制造方法
公开(公告)号：US08623727B2
公开(公告)日：2014-01-07
申请号：US13326810
申请日：2011-12-15
申请人： Jong-Han Shin , Kyung-Bo Kim
发明人： Jong-Han Shin , Kyung-Bo Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/10876 , H01L23/485 , H01L27/10855 , H01L27/10885 , H01L29/1037 , H01L29/4236 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a semiconductor device includes forming a hard mask pattern over a substrate, forming an isolation layer for defining an active region by using the hard mask pattern, forming a buried gate in and across the active region and the isolation layer over the substrate, forming an inter-layer dielectric layer over the substrate, forming a storage node contact hole that exposes the hard mask pattern by selectively etching the inter-layer dielectric layer, extending the storage node contact hole to expose the active region by removing the hard mask pattern exposed under the storage node contact hole, and forming a storage node contact plug that fills the extended storage node contact hole.
摘要翻译：一种用于制造半导体器件的方法包括在衬底上形成硬掩模图案，通过使用硬掩模图案形成用于限定有源区的隔离层，在有源区和跨衬底上的隔离层中形成掩埋栅极在衬底上形成层间电介质层，形成存储节点接触孔，通过选择性地蚀刻层间电介质层来暴露硬掩模图案，通过去除硬掩模来延伸存储节点接触孔以暴露有源区在存储节点接触孔下暴露的图案，并形成填充扩展存储节点接触孔的存储节点接触插塞。

7. 发明授权

US08404543B2 Method for fabricating semiconductor device with buried gate 有权
标题翻译：具有埋栅的半导体器件的制造方法
公开(公告)号：US08404543B2
公开(公告)日：2013-03-26
申请号：US12623719
申请日：2009-11-23
申请人： Jong-Han Shin , Cheol-Hwi Ryu , Sung-Jun Kim
发明人： Jong-Han Shin , Cheol-Hwi Ryu , Sung-Jun Kim
IPC分类号： H01L21/336
CPC分类号： H01L21/76897 , H01L21/743 , H01L27/10876 , H01L29/4236
摘要： A method for fabricating a semiconductor device with a buried gate includes: etching a substrate to form a plurality of trenches; forming a plurality of buried gates that fill lower portions of the trenches; forming a plurality of sealing layers that gap-fill upper portions of the trenches and have protrusions higher than a top surface of the substrate; forming an inter-layer insulation layer over the whole surface of the substrate including the sealing layers; and etching the inter-layer insulation layer to form a contact hole that is aligned with a space between the protrusions of the sealing layers.
摘要翻译：一种用于制造具有掩埋栅极的半导体器件的方法包括：蚀刻衬底以形成多个沟槽; 形成填充沟槽下部的多个掩埋栅极; 形成多个密封层，所述多个密封层间隙地填充所述沟槽的上部并且具有高于所述衬底的顶表面的突出部; 在包括所述密封层的所述基板的整个表面上形成层间绝缘层; 并且蚀刻层间绝缘层以形成与密封层的突起之间的空间对准的接触孔。

8. 发明申请

US20120100704A1 SEMICONDUCTOR DEVICE WITH VERTICAL TRANSISTOR AND METHOD FOR FABRICATING THE SAME 有权
公开(公告)号：US20120100704A1
公开(公告)日：2012-04-26
申请号：US13339085
申请日：2011-12-28
申请人： Jong-Han SHIN
发明人： Jong-Han SHIN
IPC分类号： H01L21/28
CPC分类号： H01L29/66666 , H01L27/10876 , H01L29/7827
摘要： A semiconductor device with a vertical transistor includes a plurality of active pillars; a plurality of vertical gates surrounding sidewalls of the active pillars; a plurality of word lines having exposed sidewalls whose surfaces are higher than the active pillars and connecting the adjacent vertical gates together; and a plurality of spacers surrounding the exposed sidewalls of the word lines over the vertical gates.

9. 发明授权

US07994056B2 Method for forming pattern in semiconductor device 失效
标题翻译：在半导体器件中形成图案的方法
公开(公告)号：US07994056B2
公开(公告)日：2011-08-09
申请号：US11965582
申请日：2007-12-27
申请人： Jong-Han Shin , Hyung-Soon Park , Cheol-Hwi Ryu , Jum-Yong Park , Sung-Jun Kim
发明人： Jong-Han Shin , Hyung-Soon Park , Cheol-Hwi Ryu , Jum-Yong Park , Sung-Jun Kim
IPC分类号： H01L21/301 , H01L21/461 , H01L21/311 , C03C15/00 , C03C25/68 , C23F1/00
CPC分类号： H01L21/0337 , H01L21/0334 , H01L27/105 , H01L27/1052 , H01L27/10894
摘要： A method for forming a pattern in a semiconductor device includes forming an etch-target layer over a substrate, wherein the substrate includes a first region having a smaller pattern than the first region, forming a sacrificial layer and a passivation layer over the etch-target layer, etching the passivation layer and the sacrificial layer to form stack structures including a sacrificial pattern and a passivation pattern, forming spacers over sidewalls of the stack structures, forming a mask pattern covering the second region, removing a portion of the passivation pattern in the first region exposed by the mask pattern to expose a portion of the sacrificial pattern in the first region, removing the exposed portion of the sacrificial pattern in the first region, and etching the etch-target layer to form an etch-target pattern using the spacers in the first and second regions and the stack structure formed between the spacers in the second region.
摘要翻译：在半导体器件中形成图案的方法包括在衬底上形成蚀刻目标层，其中衬底包括具有比第一区域更小的图案的第一区域，在蚀刻靶上形成牺牲层和钝化层蚀刻钝化层和牺牲层以形成包括牺牲图案和钝化图案的堆叠结构，在堆叠结构的侧壁上形成间隔物，形成覆盖第二区域的掩模图案，从而去除钝化层中的钝化图案的一部分第一区域由掩模图案曝光以暴露第一区域中的牺牲图案的一部分，去除第一区域中的牺牲图案的暴露部分，以及蚀刻蚀刻目标层，以使用间隔物在第一区域和第二区域中形成叠层结构，并且在第二区域中形成在间隔物之间。

10. 发明申请

US20100237405A1 SEMICONDUCTOR DEVICE WITH VERTICAL TRANSISTOR AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：具有垂直晶体管的半导体器件及其制造方法
公开(公告)号：US20100237405A1
公开(公告)日：2010-09-23
申请号：US12493176
申请日：2009-06-27
申请人： Jong-Han Shin
发明人： Jong-Han Shin
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66666 , H01L27/10876 , H01L29/7827
摘要： A semiconductor device with a vertical transistor includes a plurality of active pillars, a plurality of vertical gates surrounding sidewalls of the active pillars; a plurality of word lines having exposed sidewalls whose surfaces are higher than the active pillars and connecting the adjacent vertical gates together, and a plurality of spacers surrounding the exposed sidewalls of the word lines over the vertical gates.
摘要翻译：具有垂直晶体管的半导体器件包括多个有源支柱，围绕有源支柱侧壁的多个垂直栅极; 多个字线具有暴露的侧壁，其表面高于有源柱并将相邻的垂直栅极连接在一起，以及围绕垂直栅极的字线暴露的侧壁围绕的多个间隔物。

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