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1. 发明授权

US09064736B2 Method of manufacturing three dimensional semiconductor memory device 有权
标题翻译：制造三维半导体存储器件的方法
公开(公告)号：US09064736B2
公开(公告)日：2015-06-23
申请号：US14248003
申请日：2014-04-08
申请人： Joon-Suk Lee , Woong Lee , Hun-Hyeong Lim , Ki-Hyun Hwang
发明人： Joon-Suk Lee , Woong Lee , Hun-Hyeong Lim , Ki-Hyun Hwang
IPC分类号： H01L21/311 , H01L27/115
CPC分类号： H01L27/11578 , H01L27/1157 , H01L27/11582
摘要： A method of manufacturing a three-dimensional semiconductor memory device is provided. The method includes alternately stacking a first insulation film, a first sacrificial film, alternating second insulation films and second sacrificial films, a third sacrificial film and a third insulation film on a substrate. A channel hole is formed to expose a portion of the substrate while passing through the first insulation film, the first sacrificial film, the second insulation films, the second sacrificial films, the third sacrificial film and the third insulation film. The method further includes forming a semiconductor pattern on the portion of the substrate exposed in the channel hole by epitaxial growth. Forming the semiconductor pattern includes forming a lower epitaxial film, doping an impurity into the lower epitaxial film, and forming an upper epitaxial film on the lower epitaxial film. Forming the lower epitaxial film, doping the impurity into the lower epitaxial film and forming the upper epitaxial film are all performed in-situ, and the semiconductor pattern includes a doped region and an undoped region.
摘要翻译：提供一种制造三维半导体存储器件的方法。该方法包括在基板上交替堆叠第一绝缘膜，第一牺牲膜，交替的第二绝缘膜和第二牺牲膜，第三牺牲膜和第三绝缘膜。形成通道孔，以在穿过第一绝缘膜，第一牺牲膜，第二绝缘膜，第二牺牲膜，第三牺牲膜和第三绝缘膜的同时暴露衬底的一部分。该方法还包括通过外延生长在暴露在通道孔中的衬底的部分上形成半导体图案。形成半导体图案包括形成下部外延膜，将杂质掺杂到下部外延膜中，以及在下部外延膜上形成上部外延膜。形成下部外延膜，将杂质掺杂到下部外延膜中并形成上部外延膜全部原位进行，并且半导体图案包括掺杂区域和未掺杂区域。

2. 发明授权

US08614476B2 Nonvolatile memory devices and fabricating methods thereof 有权
标题翻译：非易失存储器件及其制造方法
公开(公告)号：US08614476B2
公开(公告)日：2013-12-24
申请号：US13564992
申请日：2012-08-02
申请人： Hong-Suk Kim , Yong-Seok Kim , Hun-Hyeong Lim , Ki-Hyun Hwang
发明人： Hong-Suk Kim , Yong-Seok Kim , Hun-Hyeong Lim , Ki-Hyun Hwang
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42336 , H01L29/66825 , H01L29/7881
摘要： Non-volatile memory devices, and fabricating methods thereof, include a floating gate over a substrate, a lower barrier layer including a first lower barrier layer on the upper surface of the floating gate, and a second lower barrier layer on a side surface of the floating gate to have a thickness smaller than a thickness of the first lower barrier layer, an inter-gate dielectric layer over the lower barrier layer, and a control gate over the inter-gate dielectric layer.
摘要翻译：非易失性存储器件及其制造方法包括在衬底上的浮置栅极，在浮置栅极的上表面上包括第一下阻挡层的下势垒层和位于浮置栅极的侧表面上的第二下势垒层浮栅的厚度小于第一下阻挡层的厚度，下阻挡层上的栅极间电介质层和栅极间电介质层上的控制栅极。

3. 发明申请

US20120187470A1 GATE STRUCTURES 有权
标题翻译：门结构
公开(公告)号：US20120187470A1
公开(公告)日：2012-07-26
申请号：US13340968
申请日：2011-12-30
申请人： Jung-Hwan KIM , Sung-Ho Heo , Jae-Ho Choi , Hun-Hyeong Lim , Ki-Hyun Hwang , Woo-Sung Lee
发明人： Jung-Hwan KIM , Sung-Ho Heo , Jae-Ho Choi , Hun-Hyeong Lim , Ki-Hyun Hwang , Woo-Sung Lee
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , H01L27/11531
摘要： A method of forming a gate structure includes forming a tunnel insulation layer pattern on a substrate, forming a floating gate on the tunnel insulation layer pattern, forming a dielectric layer pattern on the floating gate, the dielectric layer pattern including a first oxide layer pattern, a nitride layer pattern on the first oxide layer pattern, and a second oxide layer pattern on the nitride layer pattern, the second oxide layer pattern being formed by performing an anisotropic plasma oxidation process on the nitride layer, such that a first portion of the second oxide layer pattern on a top surface of the floating gate has a larger thickness than a second portion of the second oxide layer pattern on a sidewall of the floating gate, and forming a control gate on the second oxide layer.
摘要翻译：形成栅极结构的方法包括在衬底上形成隧道绝缘层图案，在隧道绝缘层图案上形成浮栅，在浮栅上形成电介质层图案，电介质层图案包括第一氧化层图案，所述第一氧化物层图案上的氮化物层图案和所述氮化物层图案上的第二氧化物层图案，所述第二氧化物层图案通过在所述氮化物层上进行各向异性等离子体氧化处理而形成，使得所述第二氧化物层图案的第二部分在浮置栅极的顶表面上的氧化物层图案具有比浮置栅极的侧壁上的第二氧化物层图案的第二部分更大的厚度，并且在第二氧化物层上形成控制栅极。

4. 发明申请

US20120115293A1 METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120115293A1
公开(公告)日：2012-05-10
申请号：US13287509
申请日：2011-11-02
申请人： Jin-Tae NOH , Hun-Hyeong Lim , Ki-Hyun Hwang , Jin-Gyun Kim , Sang-Ryol Yang
发明人： Jin-Tae NOH , Hun-Hyeong Lim , Ki-Hyun Hwang , Jin-Gyun Kim , Sang-Ryol Yang
IPC分类号： H01L21/336 , H01L21/8234 , B82Y40/00
CPC分类号： H01L27/1157 , H01L27/10855 , H01L27/11582
摘要： In a method of manufacturing a semiconductor device, a plurality of sacrificial layers and a plurality of insulating interlayers are repeatedly and alternately on a substrate. The insulating interlayers include a different material from a material of the sacrificial layers. At least one opening through the insulating interlayers and the sacrificial layers are formed. The at least one opening exposes the substrate. The seed layer is formed on an inner wall of the at least one opening using a first silicon source gas. A polysilicon channel is formed in the at least one opening by growing the seed layer. The sacrificial layers are removed to form a plurality of grooves between the insulating interlayers. A plurality of gate structures is formed in the grooves, respectively.
摘要翻译：在制造半导体器件的方法中，多个牺牲层和多个绝缘中间层在衬底上重复交替。绝缘夹层包括与牺牲层的材料不同的材料。通过绝缘夹层和牺牲层形成至少一个开口。至少一个开口露出基板。种子层使用第一硅源气体形成在至少一个开口的内壁上。通过种植种子层在至少一个开口中形成多晶硅沟道。去除牺牲层以在绝缘夹层之间形成多个凹槽。在槽中分别形成有多个栅极结构。

5. 发明授权

US09461061B2 Vertical memory devices and methods of manufacturing the same 有权
标题翻译：垂直存储器件及其制造方法
公开(公告)号：US09461061B2
公开(公告)日：2016-10-04
申请号：US14546172
申请日：2014-11-18
申请人： Phil-Ouk Nam , Jun-Kyu Yang , Jin-Gyun Kim , Jae-Young Ahn , Hun Hyeong Lim , Ki-Hyun Hwang
发明人： Phil-Ouk Nam , Jun-Kyu Yang , Jin-Gyun Kim , Jae-Young Ahn , Hun Hyeong Lim , Ki-Hyun Hwang
IPC分类号： H01L27/115 , H01L29/66 , H01L29/792
CPC分类号： H01L27/11582 , H01L29/66833 , H01L29/7926
摘要： A method of manufacturing a vertical memory device includes forming alternating and repeating insulating interlayers and sacrificial layers on a substrate, the sacrificial layers including polysilicon or amorphous silicon, forming channel holes through the insulating interlayers and the sacrificial layers, forming channels in the channel holes, etching portions of the insulating interlayers and the sacrificial layers between adjacent channels to form openings, removing the sacrificial layers to form gaps between the insulating interlayers, and forming gate lines in the gaps.
摘要翻译：制造垂直存储器件的方法包括在衬底上形成交替和重复的绝缘夹层和牺牲层，牺牲层包括多晶硅或非晶硅，通过绝缘夹层和牺牲层形成通道孔，在通道孔中形成通道，蚀刻绝缘夹层的部分和相邻通道之间的牺牲层以形成开口，去除牺牲层以在绝缘夹层之间形成间隙，并在间隙中形成栅极线。

6. 发明申请

US20140332875A1 VERTICAL MEMORY DEVICES AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：垂直存储器件及其制造方法
公开(公告)号：US20140332875A1
公开(公告)日：2014-11-13
申请号：US14184262
申请日：2014-02-19
申请人： Jung-Hwan Kim , Jun-Kyu Yang , Hun-Hyeong Lim , Jae-ho Choi , Ki-Hyun Hwang
发明人： Jung-Hwan Kim , Jun-Kyu Yang , Hun-Hyeong Lim , Jae-ho Choi , Ki-Hyun Hwang
IPC分类号： H01L27/115 , H01L21/28
CPC分类号： H01L29/7926 , H01L21/28282 , H01L27/11582 , H01L29/66833
摘要： A method of manufacturing a vertical memory device is disclosed. In the method, a plurality of insulation layers and a plurality of first sacrificial layers are alternately stacked on a substrate. A plurality of holes is formed through the plurality of insulation layers and first sacrificial layers. A plasma treatment process is performed to oxidize the first sacrificial layers exposed by the holes. A plurality of second sacrificial layer patterns project from sidewalls of the holes. A blocking layer pattern, a charge storage layer pattern and a tunnel insulation layer pattern are formed on the sidewall of the holes that cover the second sacrificial layer patterns. A plurality of channels is formed to fill the holes. The first sacrificial layers and the second sacrificial layer patterns are removed to form a plurality of gaps exposing a sidewall of the blocking layer pattern. A plurality of gate electrodes is formed to fill the gaps.
摘要翻译：公开了制造垂直存储器件的方法。在该方法中，多个绝缘层和多个第一牺牲层交替堆叠在基板上。通过多个绝缘层和第一牺牲层形成多个孔。进行等离子体处理工艺以氧化由孔暴露的第一牺牲层。多个第二牺牲层图案从孔的侧壁突出。在覆盖第二牺牲层图案的孔的侧壁上形成阻挡层图案，电荷存储层图案和隧道绝缘层图案。形成多个通道以填充孔。去除第一牺牲层和第二牺牲层图案以形成暴露阻挡层图案的侧壁的多个间隙。形成多个栅电极以填充间隙。

7. 发明授权

US08445367B2 Methods of manufacturing semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08445367B2
公开(公告)日：2013-05-21
申请号：US13287509
申请日：2011-11-02
申请人： Jin-Tae Noh , Hun-Hyeong Lim , Ki-Hyun Hwang , Jin-Gyun Kim , Sang-Ryol Yang
发明人： Jin-Tae Noh , Hun-Hyeong Lim , Ki-Hyun Hwang , Jin-Gyun Kim , Sang-Ryol Yang
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L27/1157 , H01L27/10855 , H01L27/11582
摘要： In a method of manufacturing a semiconductor device, a plurality of sacrificial layers and a plurality of insulating interlayers are repeatedly and alternately on a substrate. The insulating interlayers include a different material from a material of the sacrificial layers. At least one opening through the insulating interlayers and the sacrificial layers are formed. The at least one opening exposes the substrate. The seed layer is formed on an inner wall of the at least one opening using a first silicon source gas. A polysilicon channel is formed in the at least one opening by growing the seed layer. The sacrificial layers are removed to form a plurality of grooves between the insulating interlayers. A plurality of gate structures is formed in the grooves, respectively.
摘要翻译：在制造半导体器件的方法中，多个牺牲层和多个绝缘中间层在衬底上重复交替。绝缘夹层包括与牺牲层的材料不同的材料。通过绝缘夹层和牺牲层形成至少一个开口。至少一个开口露出基板。种子层使用第一硅源气体形成在至少一个开口的内壁上。通过种植种子层在至少一个开口中形成多晶硅沟道。去除牺牲层以在绝缘夹层之间形成多个凹槽。在槽中分别形成有多个栅极结构。

8. 发明申请

US20130105880A1 NONVOLATILE MEMORY DEVICES AND FABRICATING METHODS THEREOF 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20130105880A1
公开(公告)日：2013-05-02
申请号：US13564992
申请日：2012-08-02
申请人： Hong-Suk Kim , Yong-Seok Kim , Hun-Hyeong Lim , Ki-Hyun Hwang
发明人： Hong-Suk Kim , Yong-Seok Kim , Hun-Hyeong Lim , Ki-Hyun Hwang
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42336 , H01L29/66825 , H01L29/7881
摘要： Non-volatile memory devices, and fabricating methods thereof, include a floating gate over a substrate, a lower barrier layer including a first lower barrier layer on the upper surface of the floating gate, and a second lower barrier layer on a side surface of the floating gate to have a thickness smaller than a thickness of the first lower barrier layer, an inter-gate dielectric layer over the lower barrier layer, and a control gate over the inter-gate dielectric layer.
摘要翻译：非易失性存储器件及其制造方法包括在衬底上的浮置栅极，在浮置栅极的上表面上包括第一下阻挡层的下势垒层和位于浮置栅极的侧表面上的第二下势垒层浮栅的厚度小于第一下阻挡层的厚度，下阻挡层上的栅极间电介质层和栅极间电介质层上的控制栅极。

9. 发明授权

US08659069B2 Gate structures 有权
标题翻译：门结构
公开(公告)号：US08659069B2
公开(公告)日：2014-02-25
申请号：US13340968
申请日：2011-12-30
申请人： Jung-Hwan Kim , Sung-Ho Heo , Jae-Ho Choi , Hun-Hyeong Lim , Ki-Hyun Hwang , Woo-Sung Lee
发明人： Jung-Hwan Kim , Sung-Ho Heo , Jae-Ho Choi , Hun-Hyeong Lim , Ki-Hyun Hwang , Woo-Sung Lee
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , H01L27/11531
摘要： A method of forming a gate structure includes forming a tunnel insulation layer pattern on a substrate, forming a floating gate on the tunnel insulation layer pattern, forming a dielectric layer pattern on the floating gate, the dielectric layer pattern including a first oxide layer pattern, a nitride layer pattern on the first oxide layer pattern, and a second oxide layer pattern on the nitride layer pattern, the second oxide layer pattern being formed by performing an anisotropic plasma oxidation process on the nitride layer, such that a first portion of the second oxide layer pattern on a top surface of the floating gate has a larger thickness than a second portion of the second oxide layer pattern on a sidewall of the floating gate, and forming a control gate on the second oxide layer.
摘要翻译：形成栅极结构的方法包括在衬底上形成隧道绝缘层图案，在隧道绝缘层图案上形成浮栅，在浮栅上形成电介质层图案，电介质层图案包括第一氧化物层图案，所述第一氧化物层图案上的氮化物层图案和所述氮化物层图案上的第二氧化物层图案，所述第二氧化物层图案通过在所述氮化物层上进行各向异性等离子体氧化处理而形成，使得所述第二氧化物层图案的第二部分在浮置栅极的顶表面上的氧化物层图案具有比浮置栅极的侧壁上的第二氧化物层图案的第二部分更大的厚度，并且在第二氧化物层上形成控制栅极。

10. 发明授权

US08994091B2 Non-volatile memory device having a vertical structure and method of fabricating the same 有权
标题翻译：具有垂直结构的非易失性存储器件及其制造方法
公开(公告)号：US08994091B2
公开(公告)日：2015-03-31
申请号：US13458293
申请日：2012-04-27
申请人： Sang-Hoon Lee , Jin-Gyun Kim , Koong-Hyun Nam , Ki-Hyun Hwang , Hun-Hyeong Lim , Dong-Kyum Kim
发明人： Sang-Hoon Lee , Jin-Gyun Kim , Koong-Hyun Nam , Ki-Hyun Hwang , Hun-Hyeong Lim , Dong-Kyum Kim
IPC分类号： H01L29/76 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11582 , H01L27/11556 , H01L29/4234 , H01L29/7889 , H01L29/7926
摘要： A non-volatile memory device having a vertical structure includes a semiconductor layer, a sidewall insulation layer extending in a vertical direction on the semiconductor layer, and having one or more protrusion regions, first control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of portions of the sidewall insulation layer where the one or more protrusion regions are not formed and second control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of the one or more protrusion regions.
摘要翻译：具有垂直结构的非易失性存储器件包括半导体层，在半导体层上沿垂直方向延伸的侧壁绝缘层，并且具有一个或多个突出区域，在半导体层上沿垂直方向布置的第一控制栅电极并且分别接触在半导体层上形成有一个或多个突起区域的侧壁绝缘层的一部分和在垂直方向上排列的第二控制栅电极，并分别接触一个或多个突出区域中的一个。

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