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1. 发明授权

US08190829B2 Data processing circuit with multiplexed memory 有权
标题翻译：具有复用存储器的数据处理电路
公开(公告)号：US08190829B2
公开(公告)日：2012-05-29
申请号：US12340547
申请日：2008-12-19
申请人： Jozef L. W. Kessels , Ivan Andrejic
发明人： Jozef L. W. Kessels , Ivan Andrejic
IPC分类号： G06F13/00
CPC分类号： G06F13/1642 , G06F13/1673 , Y02D10/14
摘要： A data processing apparatus contains several processing circuits each operating under control of its own periodic clock signal, so that the clock signals may have different frequencies and/or can be autonomous. The several processing circuits each have an output for outputting memory access requests, which remain at the output for a validity duration interval defined by the clock signal of the particular processor. A multiplexing circuit multiplexes the access requests to a memory. The memory needs a minimum memory repetition period before it can accept an access request following acceptance of a preceding access request. The clock periods of the processing circuits are longer than the minimum memory repetition period. A timing circuit selects acceptance time points at which each particular access request from a first data processing circuit is accepted. The time point at which the particular request is accepted is always within the validity duration interval in which the particular access request is made. The timing circuit varies the position of the acceptance time points within the validity duration intervals, so that the position is delayed to make room for previously accepting an access request from another processor. The position is subsequently moved back toward a start of the validity duration interval in successive steps during application of successive access requests from the first data processing circuit.
摘要翻译：数据处理装置包含多个处理电路，每个处理电路在其自己的周期时钟信号的控制下操作，使得时钟信号可以具有不同的频率和/或可以是自主的。多个处理电路各自具有用于输出存储器访问请求的输出，其存储在由特定处理器的时钟信号定义的有效期间隔的输出处。复用电路将访问请求复用到存储器。存储器需要最小的存储器重复周期，才能在接受前面的访问请求之后接受访问请求。处理电路的时钟周期比最小存储器重复周期长。定时电路选择接受来自第一数据处理电路的每个特定访问请求的接收时间点。特定请求被接受的时间点总是在进行特定访问请求的有效期间隔内。定时电路在有效持续时间间隔内改变接受时间点的位置，使得位置被延迟以便先前接受来自另一处理器的访问请求的空间。随后在应用来自第一数据处理电路的连续访问请求期间，该位置在连续的步骤中向着有效持续时间间隔的开始移回。

2. 发明授权

US4686670A Method of switching time slots in a TDM-signal and arrangement for performing the method 失效
标题翻译：在TDM信号中切换时隙的方法和用于执行该方法的装置
公开(公告)号：US4686670A
公开(公告)日：1987-08-11
申请号：US785315
申请日：1985-10-07
申请人： Jozef L. W. Kessels , Alphons A. M. L. Bruekers
发明人： Jozef L. W. Kessels , Alphons A. M. L. Bruekers
IPC分类号： H04Q11/04 , G06F7/78 , H04Q11/08
CPC分类号： G06F7/78 , H04Q11/08
摘要： A time switching method and apparatus for exchanging data words from a sequence of time slots in an incoming time-division multiplex frame to any other sequence of time slots an outgoing time-division multiplex frame. A data word in a given time slot s in an incoming frame is stored in a memory at an address A(s) which is equal to the number of time slots D.sub.j in an outgoing frame for which j is less than s and for which D.sub.j exceeds D(s). The data word already in the memory location address A(s) and the data words in addresses higher than that address are each shifted to the next higher address. Data words at memory addresses lower than A(s) are maintained at such addresses.
摘要翻译：一种时间切换方法和装置，用于将输入时分复用帧中的时隙序列中的数据字与输出时分复用帧的任何其他时隙序列进行交换。在输入帧中的给定时隙中的数据字被存储在存储器中的地址A（s），其等于j小于s的输出帧中的时隙Dj的数量，并且对于哪个Dj 超过D（s）。存储器位置地址A（s）中的数据字和地址高于该地址的数据字都被移到下一个更高的地址。存储器地址低于A（s）的数据字保持在这样的地址。

3. 发明授权

US4236225A Data buffer memory of the first-in, first-out type, having a variable input and a fixed output 失效
标题翻译：先进先出型的数据缓冲存储器，具有可变输入和固定输出
公开(公告)号：US4236225A
公开(公告)日：1980-11-25
申请号：US965208
申请日：1978-11-30
申请人： Pierre G. Jansen , Jozef L. W. Kessels , Benny L. A. Waumans
发明人： Pierre G. Jansen , Jozef L. W. Kessels , Benny L. A. Waumans
IPC分类号： G06F5/06 , G06F13/38 , G11C7/00 , G06F13/00
CPC分类号： G06F5/06
摘要： A data buffer memory for the first-in, first-out type, having an input bus by which data are supplied to the buffer, and a fixed output from which data are transferred from the buffer. Each section of the buffer includes logic whereby a variable input location can be selected. Status signals are used to determine, in cooperation with signals supplied from outside the buffer, the location where data are to be written in the buffer and when these data in the buffer must be shifted to the output.
摘要翻译：用于先入先出类型的数据缓冲存储器，具有通过其向缓冲器提供数据的输入总线以及从缓冲器传送数据的固定输出。缓冲器的每个部分包括可以选择可变输入位置的逻辑。状态信号用于与缓冲器外部提供的信号一起确定要在缓冲器中写入数据的位置，以及缓冲器中的这些数据必须移到输出端。

4. 发明授权

US4222102A Data buffer memory of the "first-in, first-out" type, comprising a variable input and a variable output 失效
标题翻译： “先进先出”类型的数据缓冲存储器，包括可变输入和可变输出
公开(公告)号：US4222102A
公开(公告)日：1980-09-09
申请号：US963547
申请日：1978-11-24
申请人： Pierre G. Jansen , Jozef L. W. Kessels , Benny L. A. Waumans
发明人： Pierre G. Jansen , Jozef L. W. Kessels , Benny L. A. Waumans
IPC分类号： G06F5/06 , G06F5/10 , G06F5/14 , G11C7/00 , G11C13/00
CPC分类号： G06F5/14
摘要： A data buffer memory of the "first-in, first-out" type, having an input bus by which data are applied to the buffer and an output bus by which data are taken up from the buffer. The buffer includes logic means whereby a variable input location and a variable output location can be selected. The logic means are provided for each section of the buffer and use status signals in co-operation with signals applied from outside the buffer, to determine where data are to be written in the buffer and where data are to be read from the buffer.
摘要翻译： “先进先出”类型的数据缓冲存储器具有将数据应用于缓冲器的输入总线和从缓冲器接收数据的输出总线。缓冲器包括可以选择可变输入位置和可变输出位置的逻辑装置。为缓冲器的每个部分提供逻辑装置，并且与缓冲器外部施加的信号协同使用状态信号，以确定将数据写入缓冲器的位置以及从缓冲器读取数据的位置。

5. 发明授权

US4598385A Device for associative searching in a sequential data stream composed of data records 失效
标题翻译：用于在由数据记录组成的顺序数据流中进行关联搜索的装置
公开(公告)号：US4598385A
公开(公告)日：1986-07-01
申请号：US611911
申请日：1984-05-17
申请人： Jozef L. W. Kessels , Wijnand J. Schoenmakers , Hendrik Vrielink
发明人： Jozef L. W. Kessels , Wijnand J. Schoenmakers , Hendrik Vrielink
IPC分类号： G06F7/22 , G06F17/30
CPC分类号： G06F17/30982 , Y10S707/99933
摘要： A device for the processing of a data base consisting of a sequence of data records, having a reference memory (140) for a reference data record and a mask memory (142) for a mask data record. In reaction to the successively received data of a data record, these memories can be read in order to activate a comparison. There is provided an indicator element (160) which has a state "provisionally correct" and which is activated by a starting signal produced by the reception of a data record. If the comparison indicates that an impermissible relationship exists between the content of an element of the data record received and the corresponding element of the reference data record, the indicator element is set to the state "incorrect". The data record received is meanwhile stored in a data buffer (100,102). At the end of the reception, the state of the indicator element indicates whether or not the data record may be applied to a user. The data buffer may consist of two buffer sections, each for one complete data record, which alternately operate in a read mode and a write mode.
摘要翻译：一种用于处理由数据记录序列组成的数据库的装置，具有用于参考数据记录的参考存储器（140）和用于掩模数据记录的掩码存储器（142）。响应于连续接收的数据记录的数据，可以读取这些存储器以激活比较。提供了具有“临时正确”状态并由接收数据记录产生的启动信号激活的指示元件（160）。如果比较表示在所接收的数据记录的元素的内容与参考数据记录的相应元素之间存在不允许的关系，则指示符元素被设置为状态“不正确”。所接收的数据记录同时存储在数据缓冲器（100,102）中。在接收结束时，指示符元素的状态指示数据记录是否可以应用于用户。数据缓冲器可以由两个缓冲器部分组成，每个缓冲器部分用于一个完整的数据记录，其以读取模式和写入模式交替操作。

6. 发明授权

US4276611A Device for the control of data flows 失效
标题翻译：用于控制数据流的设备
公开(公告)号：US4276611A
公开(公告)日：1981-06-30
申请号：US30248
申请日：1979-04-16
申请人： Pierre G. Jansen , Jozef L. W. Kessels
发明人： Pierre G. Jansen , Jozef L. W. Kessels
IPC分类号： G06F5/06 , G06F7/22 , G06F7/76 , G06F13/36 , G06F15/16 , G06F15/173 , H04Q3/68 , G06F3/00
CPC分类号： G06F7/762 , G06F7/22 , G06F7/76 , H04Q3/68
摘要： A commutation device for the selective control of data transport. At least two data inputs and data outputs, each of the latter having a buffer for storing a data word. A number of possibilities of data transport can be selectively controlled, four for a single connection and two different ones for pair-wise connection. Seven input control lines are provided, two lines for receiving a signal which indicates whether information is present on the associated input line, two lines for indicating the selected output buffer, two erase lines for making a data buffer freely accessible after output of data from the data buffer, and one priority line for granting priority to one of the two input lines if both lines select the same data buffer. There are four output control lines, two lines which indicate that the data present on the input lines have been taken up in the selected output buffer, and two lines which indicate whether an output buffer contains data. The commutation device can effect the data transport itself and can be grouped in specific arrangements to form a buffer in which the data partly determine their own path.
摘要翻译：一种用于选择性控制数据传输的换向装置。至少两个数据输入和数据输出，后者具有用于存储数据字的缓冲器。可以选择性地控制数据传输的多种可能性，对于单个连接，可以有四种可能性，另外两种可用于成对连接。提供了七条输入控制线，两条线路，用于接收指示信息是否存在于相关输入线路上的信号，两条线路用于指示所选择的输出缓冲器，两条擦除线路，用于使数据缓冲区在从数据缓冲区和一条优先级线，用于如果两条线都选择相同的数据缓冲区，则优先级为两条输入线之一。有四条输出控制线，两条线表示输入线上存在的数据已经在所选择的输出缓冲器中被占用，两行表示输出缓冲器是否包含数据。换向装置可以影响数据传输本身，并且可以按照特定的布置进行分组以形成数据部分地确定其自身路径的缓冲器。

7. 发明授权

US5414651A Arithmetic unit for multiplying long integers modulo M and R.S.A. converter provided with such multiplication device 失效
标题翻译：用于乘以M和R.S.A的长整数的算术单元。转换器配有这种乘法器
公开(公告)号：US5414651A
公开(公告)日：1995-05-09
申请号：US140817
申请日：1993-10-21
申请人： Jozef L. W. Kessels
发明人： Jozef L. W. Kessels
IPC分类号： G06F7/52 , G06F7/506 , G06F7/523 , G06F7/525 , G06F7/53 , G06F7/552 , G06F7/72 , G09C1/00 , G06F7/38
CPC分类号： G06F7/722 , G06F7/723
摘要： Arithmetic unit for multiplying long integers modulo M and R.S.A. converter provided with such multiplication device.A systolized and modular arithmetic device has a control module, followed by a series arrangement of processing module, followed by a tail module. For multiplying an integer P and an integer Q modulo a third integer M, a provisional product is incremented each time with Q for a -1- bit in P, preceding by a doubling of the product. For a -0- bit only the doubling ensues. Normalizing mod M is effected by adding the complement of M, W, under control of propagated carry values. A similar procedure is proposed for exponentiation of Q. F.
摘要翻译：用于乘以M和R.S.A的长整数的算术单元。转换器配有这种乘法器。一个收缩和模数运算器具有一个控制模块，其后是一个串联的处理模块，后跟一个尾模块。为了将整数P和整数Q模数乘以第三整数M，在产品的加倍之前，临时乘积每增加一次，对于P中的1-位，Q为增量。对于-0位，只有倍增。通过在传播进位值的控制下加上M，W的补数来实现归一化mod M。提出了一种类似的Q.

8. 发明授权

US4779008A Multiple redundant clock system comprising a number of mutually synchronizing clocks, and clock circuit for use in such a clock system 失效
标题翻译：包括多个相互同步的时钟的多重冗余时钟系统和用于这种时钟系统的时钟电路
公开(公告)号：US4779008A
公开(公告)日：1988-10-18
申请号：US63542
申请日：1987-06-17
申请人： Jozef L. W. Kessels
发明人： Jozef L. W. Kessels
IPC分类号： G06F15/16 , G06F1/04 , G06F11/18 , G06F15/177 , H04J3/06 , H03K5/13 , H01J19/82
CPC分类号： G06F11/1604 , G06F11/187 , H03L7/085
摘要： A multiple redundant clock system comprises at least n=4 clocks and is self-synchronizing and fault tolerant against the failure of at the most 1/2(n-1) clocks. Each clock comprises an oscillator circuit which activates a dividing circuit at the end of each period in order to form its own clock signal on the output of the dividing circuit. Each clock furthermore comprises a deviation-determining device which compares the own clock signal with the clock signals originating from the other clocks in the system. When an excessively large number of the other clock signals deviate during the first half of the (own) period, the own oscillator circuit is decelerated. When an excessively large number of the other clock signals deviate during the second half of the own period, the own oscillator circuit is accelerated.
摘要翻译：多重冗余时钟系统至少包括n = 4个时钟，并且对于最多1/2（n-1）个时钟的故障是自同步和容错的。每个时钟包括振荡器电路，其在每个周期结束时激活分频电路，以便在分频电路的输出端形成自己的时钟信号。每个时钟还包括偏差确定装置，其将自己的时钟信号与源自系统中的其他时钟的时钟信号进行比较。当在（自身）周期的前一半期间其他时钟信号的数量过大时，自身振荡电路减速。当在其自身周期的后半段中过多的其它时钟信号偏离时，自身的振荡电路被加速。

9. 发明授权

US4769771A Multiprocessor system comprising a plurality of data processors which are interconnected by a communication network 失效
标题翻译：多处理器系统包括由通信网络互连的多个数据处理器
公开(公告)号：US4769771A
公开(公告)日：1988-09-06
申请号：US691316
申请日：1985-01-14
申请人： Wouter J. H. M. Lippmann , Jozef L. W. Kessels , Huibert H. Eggenhuisen , Hendrik Dijkstra
发明人： Wouter J. H. M. Lippmann , Jozef L. W. Kessels , Huibert H. Eggenhuisen , Hendrik Dijkstra
IPC分类号： G06F15/16 , G06F9/46 , G06F15/167 , G06F15/177
CPC分类号： G06F9/546
摘要： A processor system having one or more stations (22, 24, 26) which are interconnected by a general communication network (20). Each station has one or more processors (34, 36). Superprocesses (74, 76, 78) which have one or more processes (80-90) can be executed in the stations. Each superprocess is provided with mail-box space (50, 52, 54) for communication with the environment, in which mail-box space the relevant superprocess and other superprocesses can write but in which only the relevant superprocess itself can read. Processes within the same superprocess have variable data in common, but their register stacks are private. Each mail-box is provided with a filling indicator. In the case of a read operation in an empty mail-box space, a wait signal is issued for the initiating process; write operations in a full mail-box space produce an error signal. There is also provided a job control system for allocating jobs among the stations by way of an application load file.
摘要翻译：一种具有一个或多个通过通用网络（20）互连的站（22,24,26）的处理器系统。每个站具有一个或多个处理器（34,36）。可以在站中执行具有一个或多个处理（80-90）的超级处理（74,76,78）。每个超级处理器提供有用于与环境通信的邮箱空间（50,52,54），其中相关超级处理器和其他超级处理器可写入的邮箱空间，其中只有相关的超级处理本身可以读取。同一超级进程中的进程具有可变数据，但是它们的寄存器堆栈是私有的。每个邮箱都配有一个填充指示器。在空邮箱空间中进行读取操作的情况下，发出启动处理的等待信号。在完整的邮箱空间中写入操作会产生错误信号。还提供了一种用于通过应用加载文件在站点之间分配作业的作业控制系统。

10. 发明授权

US4553234A Method and system of transmitting digital information in a transmission ring 失效
标题翻译：在传输环中传输数字信息的方法和系统
公开(公告)号：US4553234A
公开(公告)日：1985-11-12
申请号：US566945
申请日：1983-12-30
申请人： Johan R. Brandsma , Alphons A. M. L. Bruekers , Jozef L. W. Kessels
发明人： Johan R. Brandsma , Alphons A. M. L. Bruekers , Jozef L. W. Kessels
IPC分类号： H04L5/22 , H04L12/43 , H04L12/64 , H04J3/00
CPC分类号： H04L12/64 , H04L12/43
摘要： The invention relates to a broad-band, time-division multiplex, token-passing, ring local area network, with which both circuit-switched and packet-switched traffic, namely data, text, picture and speech traffic can be supported. The invention has for its object to provide a method of transmitting digital information in a ring having a comparatively high transmission capacity with which rapid access to the common ring transmission means can be obtained, without however high requirements being imposed on the processing speed of the stations. According to the invention this is in principle achieved by means of a method which guarantees that per time-division multiplex frame only one time slot, which is known to the station, needs to be accessed.
摘要翻译：本发明涉及可以支持电路交换和分组交换业务（即数据，文本，图片和语音业务）的宽带，时分复用，令牌传递，环形局域网。本发明的目的是提供一种在具有相对高的传输容量的环中传送数字信息的方法，通过该方法可以获得对公共环传输装置的快速访问，而对站的处理速度没有高的要求。根据本发明，这主要通过一种方法来实现，该方法保证每个时分多路复用帧仅需要访问站台已知的一个时隙。

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