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    • 5. 发明授权
    • Reconfigurable processor architecture
    • 可重构的处理器架构
    • US09213677B2
    • 2015-12-15
    • US13582485
    • 2011-02-28
    • Ralf KonigTimo StripfJurgen Becker
    • Ralf KonigTimo StripfJurgen Becker
    • G06F15/00G06F15/76G06F15/78G06F15/80
    • G06F15/7867G06F15/8007
    • A reconfigurable data processor architecture. The processor architecture includes: a first plurality of data processing elements, each having a respective synchronization unit, a data link structure adapted for dynamically interconnecting a number of the data processing elements, at least one configuration register, and at least one control unit in operative connection with the configuration register for controlling a contents thereof, wherein, based on the contents, the first plurality of data processing elements is adapted for temporarily constituting at runtime at least one group of one or more of said data processing elements from said first plurality of data processing elements dynamically via the data link structure. The synchronization units are adapted for synchronizing data processing by individual data processing elements within the group. The first plurality of data processing elements may be reconfigurably grouped and thus adapted to various data processing tasks at runtime. This increases data processing efficiency.
    • 可重构数据处理器架构。 处理器架构包括:第一多个数据处理元件,每个数据处理元件各自具有相应的同步单元,数据链路结构,适于动态地互连多个数据处理元件,至少一个配置寄存器和至少一个操作的控制单元 与用于控制其内容的配置寄存器的连接,其中,基于内容,第一多个数据处理元件适于在运行时临时构成来自所述第一多个数据处理元件的至少一组一个或多个所述数据处理元件 数据处理元素通过数据链接结构动态地进行。 同步单元适于使组内的各个数据处理元件的数据处理同步。 第一多个数据处理元件可以被可重构地分组,并因此适用于运行时的各种数据处理任务。 这提高了数据处理效率。