专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09379165B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US09379165B2
公开(公告)日：2016-06-28
申请号：US14263215
申请日：2014-04-28
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Atsushi Yoshida , Hiroshi Kanno , Takayuki Tsukamoto , Takamasa Okawa , Hideyuki Tabata
IPC分类号： H01L27/10 , H01L27/105 , H01L27/24 , H01L45/00 , H01L23/532
CPC分类号： H01L27/249 , H01L23/53295 , H01L45/146 , H01L45/1683 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device according to an embodiment described below comprises: first lines arranged in a first direction perpendicular to a main surface of a substrate and extending in a second direction crossing the first direction; second lines arranged in the second direction, extending in the first direction, and intersecting the first lines; memory cells disposed at intersections of the first lines and the second lines; and an interlayer insulating film provided between the second lines. The interlayer insulating film has an air gap extending continuously in the first direction so as to intersect at least some of the first lines aligned along the first direction. The interlayer insulating film also includes an insulating film positioned above the air gap and having a curved surface that protrudes toward a direction of the substrate.
摘要翻译：根据下述实施例的半导体存储器件包括：沿垂直于衬底的主表面的第一方向布置并沿与第一方向交叉的第二方向延伸的第一线; 沿第二方向布置的第二线，沿第一方向延伸并且与第一线相交; 设置在第一线和第二线的交点处的存储单元; 以及设置在第二线之间的层间绝缘膜。层间绝缘膜具有沿着第一方向连续延伸的气隙，以使沿着第一方向排列的至少一些第一线交叉。层间绝缘膜还包括位于气隙上方的绝缘膜，并且具有朝向衬底的方向突出的弯曲表面。

2. 发明授权

US09368555B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US09368555B2
公开(公告)日：2016-06-14
申请号：US14178636
申请日：2014-02-12
申请人： Kabushiki Kaisha Toshiba
发明人： Takamasa Okawa , Takayuki Tsukamoto , Yoichi Minemura , Hiroshi Kanno , Atsushi Yoshida , Hideyuki Tabata
IPC分类号： H01L27/24 , G11C13/00 , H01L45/00
CPC分类号： H01L27/249 , G11C13/0002 , G11C13/0026 , G11C13/0069 , G11C2013/0073 , G11C2213/71 , H01L27/2454 , H01L45/04 , H01L45/12 , H01L45/1226 , H01L45/146
摘要： This semiconductor memory device comprises a memory cell array that includes: a plurality of first lines; a plurality of second lines intersecting the plurality of first lines; a plurality of memory cells each disposed at an intersection of the plurality of first lines and the plurality of second lines and including a variable resistance element; and a select transistor respectively connected to an end of the plurality of first lines. The select transistor includes a gate electrode, a gate insulating film, and a conductive layer. Moreover, one end of that conductive layer is connected to the end of the first line, and a non-linear resistance layer configured from a non-linear material is connected between the first line and the conductive layer.
摘要翻译：该半导体存储器件包括存储单元阵列，其包括：多个第一线; 与所述多个第一线相交的多个第二线; 多个存储单元，各自设置在所述多个第一线和所述多条第二线的交点处，并且包括可变电阻元件; 以及选择晶体管，其分别连接到所述多条第一线的端部。选择晶体管包括栅电极，栅极绝缘膜和导电层。此外，该导电层的一端连接到第一线的端部，并且由第一线和导电层之间连接由非线性材料构成的非线性电阻层。

3. 发明申请

US20150228337A1 SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US20150228337A1
公开(公告)日：2015-08-13
申请号：US14306843
申请日：2014-06-17
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Takamasa OKAWA , Takayuki Tsukamoto , Yoichi Minemura , Hiroshi Kanno , Atsushi Yoshida , Hideyuki Tabata
IPC分类号： G11C13/00 , G11C5/02
CPC分类号： G11C13/0035 , G11C5/02 , G11C7/18 , G11C13/0002 , G11C13/0026 , G11C29/024 , G11C2029/5006 , G11C2213/71 , H01L27/101
摘要： A semiconductor memory device comprises: first lines disposed in a first direction perpendicular to a substrate and extending in a second direction parallel to the substrate; second lines disposed in the second direction and configured to extend in the first direction, the second lines intersecting the first lines; and memory cells disposed at intersections of the first lines and the second lines and each including a variable resistance element. Furthermore, a third line extends in a third direction orthogonal to the first and second directions. A select transistor is connected between the second and third lines. A control circuit controls a voltage applied to the first and third lines, and the select transistor. The control circuit renders conductive at least one of the select transistors and thereby detect a current flowing in the third line, and determines a deterioration state of the select transistor according to a detection result.
摘要翻译：一种半导体存储器件，包括：沿垂直于衬底的第一方向设置的第一线，并沿与衬底平行的第二方向延伸; 第二线沿第二方向设置并且被配置为在第一方向上延伸，第二线与第一线相交; 以及设置在第一线和第二线的交叉点处并且每个包括可变电阻元件的存储单元。此外，第三线在与第一和第二方向正交的第三方向上延伸。选择晶体管连接在第二和第三线之间。控制电路控制施加到第一和第三线和选择晶体管的电压。控制电路使至少一个选择晶体管导通，从而检测在第三线中流动的电流，并根据检测结果确定选择晶体管的劣化状态。

4. 发明申请

US20150098261A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20150098261A1
公开(公告)日：2015-04-09
申请号：US14156613
申请日：2014-01-16
申请人： Kabushiki Kaisha Toshiba
发明人： Hideyuki Tabata , Takayuki Tsukamoto
IPC分类号： G11C5/06 , G11C13/00
CPC分类号： G11C7/1042 , G11C13/0002 , G11C13/0007 , G11C13/0061 , G11C13/0069 , G11C29/028 , G11C29/34 , G11C29/52 , G11C2013/0085 , G11C2013/0088 , G11C2213/70 , G11C2213/71
摘要： A nonvolatile semiconductor memory device comprises: a memory cell array including first interconnections, second interconnections intersecting the first interconnections, and memory cells having a variable resistance element and being provided at respective intersections of the first interconnections and the second interconnections, the memory cell array being divided into bays including a predetermined number of the memory cells; and a control circuit configured to execute a first write step and a second write step executed after the first write step at a data writing operation, wherein the control circuit is configured to change over the number of simultaneously selected bits and/or the number of simultaneously selected bays depending upon whether a write step is the first write step or the second write step.
摘要翻译：非易失性半导体存储器件包括：存储单元阵列，包括第一互连，与第一互连相交的第二互连，以及具有可变电阻元件的存储单元，并且设置在第一互连和第二互连的相应交叉处，存储单元阵列为分为包含预定数量的存储单元的托架; 以及控制电路，被配置为在数据写入操作时执行在所述第一写入步骤之后执行的第一写入步骤和第二写入步骤，其中所述控制电路被配置为改变同时选择的位的数量和/或同时的数量所选择的托架取决于写入步骤是第一写入步骤还是第二写入步骤。

5. 发明授权

US09224469B2 Semiconductor memory device and memory system 有权
标题翻译：半导体存储器件和存储器系统
公开(公告)号：US09224469B2
公开(公告)日：2015-12-29
申请号：US14305503
申请日：2014-06-16
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Yoichi Minemura , Takayuki Tsukamoto , Hiroshi Kanno , Takamasa Okawa , Atsushi Yoshida , Hideyuki Tabata
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0069 , G11C13/0064 , G11C2013/0054 , G11C2013/0076 , G11C2213/71 , G11C2213/77 , G11C2213/78 , G11C2213/79
摘要： A semiconductor memory device according to an embodiment includes a memory cell array and a control circuit. The memory cell array includes first lines and second lines intersecting each other, a third line commonly connecting to the first lines, memory cells disposed at intersections of the first lines and the second lines, respectively. The control circuit is configured to execute a state determining operation detecting a voltage of the third line, and adjust a voltage applied to the first lines and the second lines during a resetting operation or a setting operation based on a result of the state determining operation. The resetting operation raises a resistance value of the variable resistance element. The setting operation lowers the resistance value of the variable resistance element.
摘要翻译：根据实施例的半导体存储器件包括存储单元阵列和控制电路。存储单元阵列包括彼此相交的第一行和第二行，通常连接到第一行的第三行，分别设置在第一行和第二行的交叉处的存储单元。控制电路被配置为执行检测第三线的电压的状态确定操作，并且在基于状态确定操作的结果的复位操作或设置操作期间调整施加到第一线路和第二线路的电压。复位操作提高了可变电阻元件的电阻值。设定动作降低可变电阻元件的电阻值。

6. 发明申请

US20150179704A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20150179704A1
公开(公告)日：2015-06-25
申请号：US14263215
申请日：2014-04-28
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Atsushi YOSHIDA , Hiroshi Kanno , Takayuki Tsukamoto , Takamasa Okawa , Hideyuki Tabata
IPC分类号： H01L27/24 , H01L23/528 , H01L23/532 , H01L45/00
CPC分类号： H01L27/249 , H01L23/53295 , H01L45/146 , H01L45/1683 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device according to an embodiment described below comprises: first lines arranged in a first direction perpendicular to a main surface of a substrate and extending in a second direction crossing the first direction; second lines arranged in the second direction, extending in the first direction, and intersecting the first lines; memory cells disposed at intersections of the first lines and the second lines; and an interlayer insulating film provided between the second lines. The interlayer insulating film has an air gap extending continuously in the first direction so as to intersect at least some of the first lines aligned along the first direction. The interlayer insulating film also includes an insulating film positioned above the air gap and having a curved surface that protrudes toward a direction of the substrate.
摘要翻译：根据下述实施例的半导体存储器件包括：沿垂直于衬底的主表面的第一方向布置并沿与第一方向交叉的第二方向延伸的第一线; 沿第二方向布置的第二线，沿第一方向延伸并且与第一线相交; 设置在第一线和第二线的交点处的存储单元; 以及设置在第二线之间的层间绝缘膜。层间绝缘膜具有沿着第一方向连续延伸的气隙，以使沿着第一方向排列的至少一些第一线交叉。层间绝缘膜还包括位于气隙上方的绝缘膜，并且具有朝向衬底的方向突出的弯曲表面。

7. 发明授权

US09311995B2 Semiconductor memory device and control method thereof 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US09311995B2
公开(公告)日：2016-04-12
申请号：US14306843
申请日：2014-06-17
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Takamasa Okawa , Takayuki Tsukamoto , Yoichi Minemura , Hiroshi Kanno , Atsushi Yoshida , Hideyuki Tabata
IPC分类号： G11C8/08 , G11C13/00 , G11C5/02 , H01L27/10 , G11C29/02 , G11C7/18 , G11C29/50
CPC分类号： G11C13/0035 , G11C5/02 , G11C7/18 , G11C13/0002 , G11C13/0026 , G11C29/024 , G11C2029/5006 , G11C2213/71 , H01L27/101
摘要： A semiconductor memory device comprises: first lines disposed in a first direction perpendicular to a substrate and extending in a second direction parallel to the substrate; second lines disposed in the second direction and configured to extend in the first direction, the second lines intersecting the first lines; and memory cells disposed at intersections of the first lines and the second lines and each including a variable resistance element. Furthermore, a third line extends in a third direction orthogonal to the first and second directions. A select transistor is connected between the second and third lines. A control circuit controls a voltage applied to the first and third lines, and the select transistor. The control circuit renders conductive at least one of the select transistors and thereby detect a current flowing in the third line, and determines a deterioration state of the select transistor according to a detection result.
摘要翻译：一种半导体存储器件，包括：沿垂直于衬底的第一方向设置的第一线，并沿与衬底平行的第二方向延伸; 第二线沿第二方向设置并且被配置为在第一方向上延伸，第二线与第一线相交; 以及设置在第一线和第二线的交叉点处并且每个包括可变电阻元件的存储单元。此外，第三线在与第一和第二方向正交的第三方向上延伸。选择晶体管连接在第二和第三线之间。控制电路控制施加到第一和第三线以及选择晶体管的电压。控制电路使至少一个选择晶体管导通，从而检测在第三线中流动的电流，并根据检测结果确定选择晶体管的劣化状态。

8. 再颁专利

USRE45480E1 Nonvolatile semiconductor memory device and producing method thereof 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：USRE45480E1
公开(公告)日：2015-04-21
申请号：US14062661
申请日：2013-10-24
申请人： Kabushiki Kaisha Toshiba
发明人： Hiroyuki Nagashima , Hirofumi Inoue , Hideyuki Tabata , Masanori Komura , Eiji Ito
IPC分类号： H01L29/792 , H01L27/11
CPC分类号： H01L27/1116 , H01L27/0207 , H01L27/0688 , H01L27/101 , H01L27/105 , H01L27/115 , H01L27/2409 , H01L27/2418 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/147 , H01L45/1675
摘要： A cell array includes a memory cell region in which memory cells are formed and a peripheral region that is provided around the memory cell region. In the memory cell region, first lines are extended in parallel with a first direction, and the first lines are repeatedly formed at first intervals in a second direction orthogonal to the first direction. In the peripheral region, each of the first lines located at (4n−3)-th (n is a positive integer) and (4n−2)-th positions in the second direction from a predetermined position has a contact connecting portion on one end side in the first direction of the first line. In the peripheral region, each of the first lines located at (4n−1)-th and 4n-th positions in the second direction from the predetermined position has the contact connecting portion on the other end side in the first direction of the first line. The contact connecting portion is formed so as to contact a contact plug extended in a laminating direction.
摘要翻译：单元阵列包括其中形成存储器单元的存储单元区域和设置在存储单元区域周围的外围区域。在存储单元区域中，第一线与第一方向平行地延伸，并且第一线在与第一方向正交的第二方向上以第一间隔重复形成。在周边区域中，位于第（4n-3）（n是正整数）的第一线和从预定位置起的第二方向的第（4n-2）个位置中的每一个在一个上具有接触连接部分在第一行的第一个方向的端部。在周边区域中，位于距规定位置的第二方向（4n-1）和第4n位置的第一线的第一线在第一线的第一方向的另一端侧具有接触连接部。接触连接部形成为与层叠方向延伸的接触插塞接触。

9. 发明授权

US09281345B2 Resistance change type memory device with three-dimensional structure 有权
标题翻译：具有三维结构的电阻变化型存储器件
公开(公告)号：US09281345B2
公开(公告)日：2016-03-08
申请号：US14107442
申请日：2013-12-16
申请人： Kabushiki Kaisha Toshiba
发明人： Hiroshi Kanno , Yoichi Minemura , Takayuki Tsukamoto , Takamasa Okawa , Atsushi Yoshida , Hideyuki Tabata
IPC分类号： H01L29/02 , H01L27/24 , H01L45/00
CPC分类号： H01L27/2436 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/085 , H01L45/10 , H01L45/1226 , H01L45/14 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1616 , H01L45/1675
摘要： According to an embodiment, a non-volatile memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction orthogonal to the first direction. The device includes third wirings, and a first and a second memory. The third wirings extend in a third direction crossing the first direction and orthogonal to the second direction, and aligned in the second direction on both sides of the second wiring. The first memory is provided between one of third wiring pair and the second wiring, the pair of third wirings facing each other across the second wiring. The second memory is provided between another one of the third wiring pair and the second wiring. The second wiring has a block portion between a first portion in contact with the first memory and a second portion in contact with the second memory.
摘要翻译：根据实施例，非易失性存储器件包括沿第一方向延伸的第一布线，沿与第一方向正交的第二方向延伸的第二布线。该设备包括第三布线，以及第一和第二存储器。第三配线在与第一方向交叉的第三方向上延伸并且与第二方向垂直，并且在第二布线的两侧沿第二方向对齐。第一存储器设置在第三布线对和第二布线中的一个之间，所述一对第三布线跨越第二布线彼此面对。第二存储器设置在第三布线对和第二布线中的另一个之间。第二布线具有与第一存储器接触的第一部分和与第二存储器接触的第二部分之间的块部分。

10. 发明授权

US09202533B2 Nonvolatile semiconductor memory device changing the number of selected bits and/or the number of selected bays at data write operation 有权
标题翻译：非易失性半导体存储器件在数据写入操作时改变所选择的位数和/或所选择的间隔的数量
公开(公告)号：US09202533B2
公开(公告)日：2015-12-01
申请号：US14156613
申请日：2014-01-16
申请人： Kabushiki Kaisha Toshiba
发明人： Hideyuki Tabata , Takayuki Tsukamoto
IPC分类号： G11C7/10 , G11C29/34 , G11C13/00 , G11C29/02 , G11C29/52
CPC分类号： G11C7/1042 , G11C13/0002 , G11C13/0007 , G11C13/0061 , G11C13/0069 , G11C29/028 , G11C29/34 , G11C29/52 , G11C2013/0085 , G11C2013/0088 , G11C2213/70 , G11C2213/71
摘要： A nonvolatile semiconductor memory device comprises: a memory cell array including first interconnections, second interconnections intersecting the first interconnections, and memory cells having a variable resistance element and being provided at respective intersections of the first interconnections and the second interconnections, the memory cell array being divided into bays including a predetermined number of the memory cells; and a control circuit configured to execute a first write step and a second write step executed after the first write step at a data writing operation, wherein the control circuit is configured to change over the number of simultaneously selected bits and/or the number of simultaneously selected bays depending upon whether a write step is the first write step or the second write step.
摘要翻译：非易失性半导体存储器件包括：存储单元阵列，包括第一互连，与第一互连相交的第二互连，以及具有可变电阻元件的存储单元，并且设置在第一互连和第二互连的相应交叉处，存储单元阵列为分为包含预定数量的存储单元的托架; 以及控制电路，被配置为在数据写入操作时执行在所述第一写入步骤之后执行的第一写入步骤和第二写入步骤，其中所述控制电路被配置为改变同时选择的位的数量和/或同时的数量所选择的托架取决于写入步骤是第一写入步骤还是第二写入步骤。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式