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    • 2. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US09478301B1
    • 2016-10-25
    • US15066718
    • 2016-03-10
    • KABUSHIKI KAISHA TOSHIBA
    • Kiichi TachiMasanobu ShirakawaMasaki YoshimuraMarie TakadaYoshikazu Harada
    • G11C11/34G11C16/26G11C16/04G11C16/14
    • G11C16/26G11C11/5628G11C11/5642G11C16/0483G11C16/10G11C16/3427G11C29/021G11C29/028
    • A semiconductor memory device according to an embodiment includes a control circuit, during data write to a memory cell, sequentially executing: an erasing stage in which a threshold value of the memory cell is transitioned into an erase distribution; a preliminary programming stage in which the threshold value is transitioned into a temporal distribution corresponding to write data; and a main programming stage in which the threshold value is transitioned into a program distribution corresponding to the write data, and the control circuit executing a main reading stage, during the data read to a first memory cell, which includes a main reading step of adjusting a read pass voltage to be applied to a neighboring word line based on a magnitude of a threshold value of the neighboring memory cell, and reading whether the first memory cell is an erase level.
    • 根据实施例的半导体存储器件包括控制电路,在对存储器单元的数据写入期间,顺次地执行:擦除阶段,其中存储单元的阈值转变为擦除分布; 初步编程阶段,其中阈值被转换成对应于写入数据的时间分布; 以及主编程阶段,其中在对第一存储单元的数据读取期间,阈值转变为对应于写入数据的程序分布,以及控制电路执行主读取级,其包括主要读取步骤 基于相邻存储单元的阈值的大小,读取相邻字线的读通过电压,以及读取第一存储单元是否为擦除电平。