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1. 发明授权

US09679651B2 Semiconductor memory device capable of determining an initial program condition for different memory cells 有权
公开(公告)号：US09679651B2
公开(公告)日：2017-06-13
申请号：US14633033
申请日：2015-02-26
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Masanobu Shirakawa
IPC分类号： G11C16/10 , G11C16/04 , G11C11/56
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483
摘要： A semiconductor memory device includes a first memory string including a first memory cell and a second memory cell, a second memory string including a third memory cell, a bit line connected to both one end of the first memory string and one end of the second memory string, a first word line connected to gates of the first and third memory cells, a second word line connected to a gate of the second memory cell, and a control circuit configured to determine a program condition of the first memory cell that have been selected for a write operation, and perform the write operation for the third memory cell based on the program condition of the first memory cell.

2. 发明授权

US09653156B2 Memory controller, nonvolatile semiconductor memory device and memory system 有权
公开(公告)号：US09653156B2
公开(公告)日：2017-05-16
申请号：US14712017
申请日：2015-05-14
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Masanobu Shirakawa , Tsuyoshi Atsumi , Hidetaka Tsuji , Tomoyuki Kantani , Hideaki Yamamoto , Yasuhiko Kurosawa
IPC分类号： G11C11/56 , G11C7/04
CPC分类号： G11C11/5642 , G11C7/04
摘要： According to one embodiment, a memory system includes a nonvolatile semiconductor memory and a memory controller. The memory controller has a first signal generation section that generates a first signal related with a read voltage used for read operation of the nonvolatile semiconductor memory, a second signal generation section that generates a second signal that specifies the temperature coefficient used for the correction for temperature of the read voltage, and a first interface section that outputs the first signal, the second signal and a read command. The nonvolatile semiconductor memory has a word line, a memory cell array includes memory cells connected to the word line, and a second interface section that receives the first signal, the second signal and the read command.

3. 发明授权

US09633745B2 Semiconductor memory device 有权
公开(公告)号：US09633745B2
公开(公告)日：2017-04-25
申请号：US15185671
申请日：2016-06-17
申请人： Kabushiki Kaisha Toshiba
发明人： Kenichi Abe , Masanobu Shirakawa , Mizuho Yoshida , Takuya Futatsuyama
IPC分类号： G11C16/04 , G11C16/34 , G11C11/56 , G11C16/10 , G11C16/32 , G11C16/08 , G11C16/16 , G11C29/42
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/32 , G11C16/3445 , G11C16/3481 , G11C29/42 , G11C2211/5621 , G11C2211/5648
摘要： A semiconductor memory device includes: first to third pages; first to third word line; and row decoder. In data writing, data is written into the first page before data is written into the second page. The row decoder is configured to apply first to third verify voltages to the gates of the first to third memory cells in a program verify operation.

4. 发明授权

US09478301B1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US09478301B1
公开(公告)日：2016-10-25
申请号：US15066718
申请日：2016-03-10
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kiichi Tachi , Masanobu Shirakawa , Masaki Yoshimura , Marie Takada , Yoshikazu Harada
IPC分类号： G11C11/34 , G11C16/26 , G11C16/04 , G11C16/14
CPC分类号： G11C16/26 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/3427 , G11C29/021 , G11C29/028
摘要： A semiconductor memory device according to an embodiment includes a control circuit, during data write to a memory cell, sequentially executing: an erasing stage in which a threshold value of the memory cell is transitioned into an erase distribution; a preliminary programming stage in which the threshold value is transitioned into a temporal distribution corresponding to write data; and a main programming stage in which the threshold value is transitioned into a program distribution corresponding to the write data, and the control circuit executing a main reading stage, during the data read to a first memory cell, which includes a main reading step of adjusting a read pass voltage to be applied to a neighboring word line based on a magnitude of a threshold value of the neighboring memory cell, and reading whether the first memory cell is an erase level.
摘要翻译：根据实施例的半导体存储器件包括控制电路，在对存储器单元的数据写入期间，顺次地执行：擦除阶段，其中存储单元的阈值转变为擦除分布; 初步编程阶段，其中阈值被转换成对应于写入数据的时间分布; 以及主编程阶段，其中在对第一存储单元的数据读取期间，阈值转变为对应于写入数据的程序分布，以及控制电路执行主读取级，其包括主要读取步骤基于相邻存储单元的阈值的大小，读取相邻字线的读通过电压，以及读取第一存储单元是否为擦除电平。

5. 发明授权

US09396775B2 Semiconductor memory device including a control circuit and at least two memory cell arrays 有权
标题翻译：半导体存储器件包括控制电路和至少两个存储单元阵列
公开(公告)号：US09396775B2
公开(公告)日：2016-07-19
申请号：US14475493
申请日：2014-09-02
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Masanobu Shirakawa , Tokumasa Hara
IPC分类号： G06F12/00 , G11C7/10 , G06F12/08 , G06F13/16 , G11C7/24
CPC分类号： G06F3/061 , G06F3/0634 , G06F3/0656 , G06F3/0659 , G06F3/0679 , G06F12/0875 , G06F13/16 , G06F2212/1016 , G06F2212/214 , G06F2212/452 , G06F2212/7203 , G06F2212/7207 , G11C7/1063 , G11C7/24 , G11C16/10 , G11C16/26
摘要： A memory device includes first and second memory cell arrays, and a control circuit configured to output first information indicating whether the first memory cell array is in a ready state in which the control circuit is ready to receive a command to access the first memory cell array or a busy state in which the control circuit is not ready to receive the command to access the first memory cell array, and second information indicating whether the second memory cell array is in a ready state in which the control circuit is ready to receive a command to access the second memory cell array or a busy state in which the control circuit is not ready to receive the command to access the second memory cell array.
摘要翻译：存储器件包括第一和第二存储单元阵列，以及控制电路，被配置为输出指示第一存储单元阵列是否处于就绪状态的第一信息，其中控制电路准备好接收访问第一存储单元阵列的命令或控制电路未准备好接收访问第一存储单元阵列的命令的忙状态，以及指示第二存储单元阵列是否处于就绪状态的第二信息，其中控制电路准备好接收命令以访问第二存储器单元阵列或其中控制电路未准备好接收用于访问第二存储单元阵列的命令的忙状态。

6. 发明授权

US09349464B2 Non-volatile semiconductor device 有权
公开(公告)号：US09349464B2
公开(公告)日：2016-05-24
申请号：US14607612
申请日：2015-01-28
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Hidehiro Shiga , Masanobu Shirakawa
IPC分类号： G11C16/04 , G11C16/14 , G11C16/34 , G11C16/08 , H01L27/115
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/08 , G11C16/3436 , G11C16/3445 , H01L27/11573 , H01L27/11582
摘要： A non-volatile semiconductor device includes first and second selecting transistors; multiple memory cells that are stacked above the substrate; multiple word lines that are connected to control gates of the multiple memory cells; selecting gate lines that are each connected to a gate of one of the selecting transistors; a bit line connected to the first selecting transistor; a source line connected to the second selecting transistor; and a control circuit configured to execute an erasing loop that includes an erase operation and a verifying operation. The control circuit increases an erasing voltage in accordance with the number of times the erasing loop is repeated.

7. 发明授权

US09214238B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US09214238B2
公开(公告)日：2015-12-15
申请号：US14474307
申请日：2014-09-02
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Takuya Futatsuyama , Masanobu Shirakawa , Kenichi Abe
IPC分类号： G11C16/10 , G11C16/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5671 , G11C16/0483 , G11C16/3459 , H01L27/11582
摘要： A semiconductor memory device includes first to fourth memory cells that are stacked above a semiconductor substrate, first to fourth word lines that are connected to gates of the first to fourth memory cells, respectively, and a row decoder that applies voltages to the first to fourth word lines. The row decoder applies a first programming voltage to the first word line during a write operation performed on the first memory cell, applies the first programming voltage to the second word line during a write operation performed on the second memory cell, applies a second programming voltage to the third word line during a write operation performed on the third memory cell, and applies the second programming voltage to the fourth word line during a write operation performed on the fourth memory cell. The second programming voltage is higher than the first programming voltage.
摘要翻译：一种半导体存储器件包括堆叠在半导体衬底之上的第一至第四存储单元，分别连接到第一至第四存储单元的栅极的第一至第四字线以及向第一至第四存储单元施加电压的行解码器字线。行解码器在对第一存储单元执行的写入操作期间向第一字线施加第一编程电压，在对第二存储单元执行的写入操作期间将第一编程电压施加到第二字线，施加第二编程电压在对第三存储器单元执行的写入操作期间将第二编程电压施加到第四字线，并且在对第四存储器单元执行的写入操作期间将第二编程电压施加到第四字线。第二编程电压高于第一编程电压。

8. 发明申请

US20130329494A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20130329494A1
公开(公告)日：2013-12-12
申请号：US13783374
申请日：2013-03-03
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Masanobu Shirakawa
IPC分类号： G11C16/06
CPC分类号： G11C16/06 , G11C16/0483 , G11C16/20 , G11C29/025 , G11C29/026 , G11C29/44 , G11C29/789 , G11C29/808 , G11C29/846 , G11C2029/1204 , G11C2029/4402
摘要： A non-volatile semiconductor memory device has memory cell arrays, with the memory cells arranged in a matrix configuration and divided into p areas in the column direction, a column redundancy area arranged in a portion of the memory cell array and having redundancy columns that can substitute for defective user data columns, and a column substituting register that holds the column substituting information for substituting the defective user data columns of the selected area with the redundancy columns.
摘要翻译：非易失性半导体存储器件具有存储单元阵列，其中存储器单元以矩阵配置排列并且在列方向上分为p个区域，列冗余区域布置在存储单元阵列的一部分中并且具有可冗余列代替有缺陷的用户数据列，以及列替换寄存器，该列替换寄存器保存列替换信息，用冗余列代替所选区域的有缺陷的用户数据列。

9. 发明授权

US09627077B2 Semiconductor memory device storing management data redundantly in different pages 有权
公开(公告)号：US09627077B2
公开(公告)日：2017-04-18
申请号：US14811524
申请日：2015-07-28
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Masanobu Shirakawa
IPC分类号： G11C16/04 , G11C16/16 , G11C16/26 , G11C16/08 , G11C16/20 , G11C29/00
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/08 , G11C16/20 , G11C16/26 , G11C29/82
摘要： A semiconductor memory device includes a memory cell array that is capable of storing data in a nonvolatile manner, and a control section that controls data access to the memory cell array. The memory cell array stores the same data redundantly in a plurality of pages. The control section executes a reading operation on the plurality of pages that store the same data redundantly to read the data. The data that is stored redundantly may be management data or user data.

10. 发明申请

US20160267980A1 SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM 有权
标题翻译：半导体存储器件和存储器系统
公开(公告)号：US20160267980A1
公开(公告)日：2016-09-15
申请号：US14847086
申请日：2015-09-08
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Takayuki AKAMINE , Masanobu Shirakawa , Hiroshi Sukegawa
IPC分类号： G11C16/04 , G11C29/02 , G11C16/10
CPC分类号： G11C16/0483 , G11C16/08 , G11C16/10 , G11C29/025 , G11C29/42 , G11C29/44 , G11C2029/0409 , G11C2029/1202 , G11C2029/5006
摘要： A semiconductor memory device includes: a first string unit including first and second memory cell transistors; a second string unit including third and fourth memory cell transistors; a first word line coupled to gates of the first and third memory cell transistors; and a second word line coupled to gates of the second and fourth memory cell transistors. When the first string unit is selected and the first word line is selected, a first voltage is applied. The first voltage is larger than an initial value of the voltage in the step-up operation.
摘要翻译：半导体存储器件包括：第一串单元，包括第一和第二存储单元晶体管; 包括第三和第四存储单元晶体管的第二串单元; 耦合到第一和第三存储单元晶体管的栅极的第一字线; 以及耦合到第二和第四存储单元晶体管的栅极的第二字线。当选择第一串单元并选择第一字线时，施加第一电压。第一电压大于升压动作时的电压的初始值。

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