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1. 发明申请

US20150295174A1 METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：制造半导体存储器件和半导体存储器件的方法
公开(公告)号：US20150295174A1
公开(公告)日：2015-10-15
申请号：US14748335
申请日：2015-06-24
申请人： Kabushiki Kaisha Toshiba
发明人： Masaki YAMATO , Takeshi YAMAGUCHI , Shigeki KOBAYASHI
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L27/2481 , H01L27/2463 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/1616 , H01L45/1683
摘要： According to one embodiment, a manufacturing method of a semiconductor memory device includes forming a stacked body in which word line material layers and insulating layers are alternately stacked on a base layer. The method includes forming first holes on the stacked body so as to be arranged in a first direction and in a second direction that intersects with the first direction. The method includes forming resistance-change films on inner walls of the first holes, forming bit lines inside the resistance-change films in the first holes, and dividing the stacked body in the first direction by forming second holes so that a portion in the stacked body adjacent to the resistance-change films in the second direction. The method includes forming inter-bit line insulating films in the second holes.
摘要翻译：根据一个实施例，半导体存储器件的制造方法包括：形成层叠体，其中字线材料层和绝缘层交替堆叠在基底层上。该方法包括在层叠体上形成第一孔，使其沿与第一方向相交的第一方向和第二方向排列。该方法包括在第一孔的内壁上形成电阻变化膜，在第一孔中的电阻变化膜内形成位线，并且通过形成第二孔而将堆叠体沿第一方向分割，使得层叠的部分与第二方向上的电阻变化膜相邻的主体。该方法包括在第二孔中形成位线间绝缘膜。

2. 发明申请

US20150155333A1 NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20150155333A1
公开(公告)日：2015-06-04
申请号：US14208204
申请日：2014-03-13
申请人： Kabushiki Kaisha Toshiba
发明人： Shigeki KOBAYASHI , Takeshi YAMAGUCHI , Masaki YAMATO , Yoshinori NAKAKUBO , Hiroyuki ODE
IPC分类号： H01L27/24 , G11C13/00 , H01L45/00
CPC分类号： H01L27/249 , G11C13/0007 , G11C13/0069 , G11C2013/0071 , H01L27/2454 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L45/148 , H01L45/149 , H01L45/16
摘要： According to an embodiment, a nonvolatile memory device includes a first wiring extending to a first direction, a second wiring disposed on the first wiring in a second direction which is orthogonal to the first direction, a first insulating film provided between the first wiring and the second wiring, a bit line extending in the second direction, and a variable resistance film contacting an end portion of the first wiring, an end portion of the second wiring, and an end portion of the first insulating film. A dielectric constant of a center portion between the first and second wirings in the second direction is higher than at vicinities of the first and the second wirings. The variable resistance film is disposed between the bit line and the first wiring, between the bit line and the second wiring, and between the bit line and the first insulating film.
摘要翻译：根据实施例，非易失性存储器件包括延伸到第一方向的第一布线，在与第一方向正交的第二方向上布置在第一布线上的第二布线，设置在第一布线和第二布线之间的第一绝缘膜第二布线，沿第二方向延伸的位线，以及与第一布线的端部，第二布线的端部和第一绝缘膜的端部接触的可变电阻膜。第一和第二布线之间的第二方向上的中心部分的介电常数高于第一和第二布线附近的介电常数。可变电阻膜设置在位线和第一布线之间，位线和第二布线之间以及位线和第一绝缘膜之间。

3. 发明申请

US20170133586A1 SEMICONDUCTOR MEMORY DEVICE 有权
公开(公告)号：US20170133586A1
公开(公告)日：2017-05-11
申请号：US15412171
申请日：2017-01-23
申请人： Kabushiki Kaisha Toshiba
发明人： Masaki YAMATO , Yasuhiro NOJIRI , Shigeki KOBAYASHI , Hiroyuki FUKUMIZU , Takeshi YAMAGUCHI
IPC分类号： H01L45/00 , G11C13/00 , H01L27/24
CPC分类号： H01L27/249 , H01L27/2454 , H01L27/2472 , H01L45/04 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/146
摘要： A plurality of first conductive layers are stacked at a predetermined pitch in a first direction perpendicular to a substrate. A memory layer is provided in common on side surfaces of the first conductive layers and functions as the memory cells. A second conductive layer comprises a first side surface in contact with side surfaces of the first conductive layers via the memory layer, the second conductive layer extending in the first direction. A width in a second direction of the first side surface at a first position is smaller than a width in the second direction of the first side surface at a second position lower than the first position. A thickness in the first direction of the first conductive layer at the first position is larger than a thickness in the first direction of the first conductive layer at the second position.

4. 发明申请

US20150108420A1 RESISTANCE CHANGE ELEMENT AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：电阻变化元件及其制造方法
公开(公告)号：US20150108420A1
公开(公告)日：2015-04-23
申请号：US14188892
申请日：2014-02-25
申请人： Kabushiki Kaisha Toshiba
发明人： Hiroyuki ODE , Takeshi YAMAGUCHI , Masaki YAMATO , Shigeki KOBAYASHI , Yoshinori NAKAKUBO
IPC分类号： H01L45/00
CPC分类号： H01L45/146 , H01L27/2481 , H01L27/249 , H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/1608
摘要： According to one embodiment, a resistance change element includes: a first electrode; a second electrode; and a resistance change film provided between the first electrode and the second electrode, and the resistance change film including: a first transition metal oxide-containing layer; a second transition metal oxide-containing layer; and an intermediate layer provided between the first transition metal oxide-containing layer and the second transition metal oxide-containing layer, the intermediate layer having a higher crystallization temperature than the first transition metal oxide-containing layer and the second transition metal oxide-containing layer, and the intermediate layer including an amorphous material.
摘要翻译：根据一个实施例，电阻变化元件包括：第一电极; 第二电极; 以及设置在所述第一电极和所述第二电极之间的电阻变化膜，所述电阻变化膜包括：第一过渡金属氧化物含有层; 第二过渡金属氧化物层; 以及设置在所述第一过渡金属氧化物含有层和所述第二过渡金属氧化物含有层之间的中间层，所述中间层的结晶温度高于所述第一过渡金属氧化物含有层和所述第二过渡金属氧化物含有层，中间层包括无定形材料。

5. 发明申请

US20140036571A1 SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20140036571A1
公开(公告)日：2014-02-06
申请号：US13848969
申请日：2013-03-22
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Shigeki KOBAYASHI , Takeshi YAMAGUCHI
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C7/22 , G11C11/00 , G11C13/0004 , G11C13/0021 , G11C13/0026 , G11C13/0028 , G11C13/0064 , G11C13/0069 , G11C2013/0054 , G11C2013/0057 , G11C2213/71 , G11C2213/72
摘要： A semiconductor memory device according to an embodiment includes a control circuit configured to apply a first voltage to a selected first line, apply a second voltage to a selected second line, and apply a third voltage and a fourth voltage to a non-selected first line and a non-selected second line in a setting operation, respectively. The control circuit includes a detection circuit configured to detect a transition of a resistance state of a selected memory cell using a reference voltage. The control circuit is configured to execute a read operation in which the control circuit applies the third voltage to the selected first line and the non-selected first line, applies the second voltage to the selected second line, and applies the fourth voltage to the non-selected second line, and set the reference voltage based on a voltage value of the selected second line.
摘要翻译：根据实施例的半导体存储器件包括：控制电路，被配置为将第一电压施加到所选择的第一线，向所选择的第二线施加第二电压，并将第三电压和第四电压施加到未选择的第一线和设置操作中的未选择的第二行。控制电路包括检测电路，其被配置为使用参考电压来检测所选存储单元的电阻状态的转变。控制电路被配置为执行读取操作，其中控制电路将第三电压施加到所选择的第一行和未选择的第一行，将第二电压施加到所选择的第二行，并将第四电压施加到非选择的第二行， - 选择的第二行，并且基于所选择的第二行的电压值设置参考电压。

6. 发明申请

US20170243883A1 SEMICONDUCTOR MEMORY DEVICE 有权
公开(公告)号：US20170243883A1
公开(公告)日：2017-08-24
申请号：US15257237
申请日：2016-09-06
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Shigeki KOBAYASHI , Atsushi KONNO
IPC分类号： H01L27/115 , H01L23/522 , H01L29/10
CPC分类号： H01L27/11582 , H01L23/5226 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L28/00 , H01L29/1087
摘要： According to an embodiment, a semiconductor memory device comprises a substrate, a plurality of first conductive layers, a memory columnar body, a first semiconductor layer, a second semiconductor layer and a contact. The plurality of first conductive layers are stacked upwardly of the substrate. The memory columnar body extends in a first direction intersecting an upper surface of the substrate and a side surface of the memory columnar body is covered by the first conductive layers. The first semiconductor layer is connected to a lower end of the memory columnar body and extends in a second direction intersecting the first direction. The second conductive layer is provided between the first semiconductor layer and the first conductive layers. The second conductive layer is connected to the memory columnar body and extending in the second direction. The contact is connected to the second conductive layer and extends in the first direction.

7. 发明申请

US20170243873A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
公开(公告)号：US20170243873A1
公开(公告)日：2017-08-24
申请号：US15269082
申请日：2016-09-19
申请人： Kabushiki Kaisha Toshiba
发明人： Shigeki KOBAYASHI , Satoshi KONAGAI , Atsushi KONNO , Kenta YAMADA , Masaaki HIGUCHI , Masao SHINGU , Soichiro KITAZAKI , Yoshimasa MIKAJIRI
IPC分类号： H01L27/115 , H01L29/51 , H01L21/768 , H01L21/285 , H01L21/28 , H01L29/423 , H01L29/49
CPC分类号： H01L27/11582 , H01L21/28088 , H01L21/28114 , H01L21/28158 , H01L21/28556 , H01L21/76831 , H01L28/00 , H01L29/42324 , H01L29/4234 , H01L29/42364 , H01L29/42376 , H01L29/4966 , H01L29/518
摘要： According to an embodiment, a semiconductor memory device comprises: a stacked body including control gate electrodes stacked upwardly of a substrate; a semiconductor layer facing the control gate electrodes; and a gate insulating layer provided between the control gate electrode and the semiconductor layer. The stacked body comprises: a first metal layer configuring the control gate electrode; a first barrier metal layer contacting an upper surface of this first metal layer; a first silicon nitride layer contacting an upper surface of this first barrier metal layer; a first inter-layer insulating layer contacting an upper surface of this first silicon nitride layer; a second barrier metal layer contacting a lower surface of the first metal layer; a second silicon nitride layer contacting a lower surface of this second barrier metal layer; and a second inter-layer insulating layer contacting a lower surface of this second silicon nitride layer.

8. 发明申请

US20160254319A1 METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE 有权
公开(公告)号：US20160254319A1
公开(公告)日：2016-09-01
申请号：US15149494
申请日：2016-05-09
申请人： Kabushiki Kaisha Toshiba
发明人： Masaki YAMATO , Takeshi YAMAGUCHI , Shigeki KOBAYASHI
IPC分类号： H01L27/24 , H01L45/00
CPC分类号： H01L27/2481 , H01L27/2463 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/1616 , H01L45/1683
摘要： According to one embodiment, a manufacturing method of a semiconductor memory device includes forming a stacked body in which word line material layers and insulating layers are alternately stacked on a base layer. The method includes forming first holes on the stacked body so as to be arranged in a first direction and in a second direction that intersects with the first direction. The method includes forming resistance-change films on inner walls of the first holes, forming bit lines inside the resistance-change films in the first holes, and dividing the stacked body in the first direction by forming second holes so that a portion in the stacked body adjacent to the resistance-change films in the second direction. The method includes forming inter-bit line insulating films in the second holes.

9. 发明申请

US20150263278A1 MEMORY DEVICE 审中-公开
标题翻译：内存设备
公开(公告)号：US20150263278A1
公开(公告)日：2015-09-17
申请号：US14490938
申请日：2014-09-19
申请人： Kabushiki Kaisha Toshiba
发明人： Hiroyuki ODE , Takeshi YAMAGUCHI , Shigeki KOBAYASHI , Masaki YAMATO , Yoshinori NAKAKUBO , Takeshi TAKAGI , Takayuki TSUKAMOTO
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L27/249 , H01L27/2454 , H01L45/04 , H01L45/1233
摘要： A memory device according to an embodiment, includes a selection element, a first interconnection provided in a first direction when viewed from the selection element and extending in the first direction, a plurality of second interconnections provided in a second direction crossing the first direction when viewed from the first interconnection and arranged in the first direction, a memory element provided between the first interconnection and the second interconnection, and a high resistance component connected between the selection element and the first interconnection and having a resistivity higher than a resistivity of the first interconnection and a resistivity of the second interconnection.
摘要翻译：根据实施例的存储器件包括选择元件，当从选择元件观察并沿第一方向延伸时设置在第一方向上的第一互连件，当被观察时沿与第一方向交叉的第二方向设置的多个第二互连设置在第一互连和第二互连之间的存储元件和连接在选择元件与第一互连之间并具有高于第一互连电阻率的电阻率的高电阻元件和第二互连的电阻率。

10. 发明申请

US20140241037A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20140241037A1
公开(公告)日：2014-08-28
申请号：US14021052
申请日：2013-09-09
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Shigeki KOBAYASHI , Yasuhiro Nojiri , Masaki Yamato , Hiroyuki Fukumizu , Takeshi Yamaguchi
IPC分类号： G11C13/00
CPC分类号： G11C13/0007 , G11C13/0023 , G11C13/0038 , G11C13/0069 , G11C19/00 , G11C2213/71 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146
摘要： A memory cell array includes first wiring lines, and second wiring lines, the first and second wiring lines intersecting, and memory cells disposed in the intersections of the first and second wiring lines, the memory cells including a variable resistance element. A control circuit controls voltages of selected first and second wiring lines. The first wiring lines are arranged at a first pitch in a first direction perpendicular to a substrate and extend in a second direction parallel to the substrate. The second wiring lines are arranged at a second pitch in the second direction and extend in the first direction. The control circuit is configured to change voltages applied to a selected first wiring line according to the positions of the selected first wiring lines in the first direction.
摘要翻译：存储单元阵列包括第一布线，第二布线，第一布线和第二布线相交，以及设置在第一布线和第二布线的交叉点中的存储单元，存储单元包括可变电阻元件。控制电路控制所选择的第一和第二布线的电压。第一布线沿垂直于基板的第一方向以第一间距布置，并且在平行于基板的第二方向上延伸。第二布线沿第二方向以第二间距布置，并沿第一方向延伸。控制电路被配置为根据所选择的第一布线在第一方向上的位置来改变施加到所选择的第一布线的电压。

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