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1. 发明授权

US09728585B1 Semiconductor memory device 有权
公开(公告)号：US09728585B1
公开(公告)日：2017-08-08
申请号：US15270682
申请日：2016-09-20
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Masaki Yamato , Takeshi Yamaguchi , Takeshi Takagi , Natsuki Fukuda
IPC分类号： H01L47/00 , H01L27/24 , H01L23/528 , H01L45/00
CPC分类号： H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/1233 , H01L45/1273 , H01L45/146 , H01L45/1683
摘要： A semiconductor memory device according to an embodiment includes: a semiconductor substrate which extends in first and second directions that intersect each other; a plurality of first wiring lines which are arranged in a third direction that intersects the first direction and the second direction, and which extend in the first direction; a plurality of second wiring lines which are arranged in the first direction and extend in the third direction; and a plurality of memory cells disposed at intersections of the first wiring lines and the second wiring lines, one of the memory cells having a first film whose resistance changes electrically, a thickness in the second direction of the first film changing with respect to a change of position in the third direction, and the first films of two of the memory cells adjacent in the third direction being separated between the two memory cells.

2. 发明授权

US09590016B2 3D semiconductor memory device having variable resistance memory elements 有权
标题翻译：具有可变电阻存储元件的3D半导体存储器件
公开(公告)号：US09590016B2
公开(公告)日：2017-03-07
申请号：US14966184
申请日：2015-12-11
申请人： Kabushiki Kaisha Toshiba
发明人： Masaki Yamato , Yasuhiro Nojiri , Shigeki Kobayashi , Hiroyuki Fukumizu , Takeshi Yamaguchi
IPC分类号： H01L27/24 , H01L45/00
CPC分类号： H01L27/249 , H01L27/2454 , H01L27/2472 , H01L45/04 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/146
摘要： A plurality of first conductive layers are stacked at a predetermined pitch in a first direction perpendicular to a substrate. A memory layer is provided in common on side surfaces of the first conductive layers and functions as the memory cells. A second conductive layer comprises a first side surface in contact with side surfaces of the first conductive layers via the memory layer, the second conductive layer extending in the first direction. A width in a second direction of the first side surface at a first position is smaller than a width in the second direction of the first side surface at a second position lower than the first position. A thickness in the first direction of the first conductive layer at the first position is larger than a thickness in the first direction of the first conductive layer at the second position.
摘要翻译：多个第一导电层以垂直于基板的第一方向以预定间距堆叠。在第一导电层的侧表面上共同提供存储层，并且用作存储单元。第二导电层包括经由存储层与第一导电层的侧表面接触的第一侧表面，第二导电层沿第一方向延伸。在第一位置处的第一侧表面的第二方向上的宽度小于在比第一位置低的第二位置处的第一侧表面的第二方向上的宽度。第一导电层在第一位置的第一方向上的厚度大于第二导电层在第二位置的第一方向上的厚度。

3. 发明授权

US09007809B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US09007809B2
公开(公告)日：2015-04-14
申请号：US13778762
申请日：2013-02-27
申请人： Kabushiki Kaisha Toshiba
发明人： Hiroyuki Fukumizu , Shigeki Kobayashi , Yasuhiro Nojiri , Masaki Yamato , Takeshi Yamaguchi
IPC分类号： G11C13/00 , H01L45/00 , H01L27/24
CPC分类号： G11C13/0002 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2013/0083 , G11C2213/52 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/146
摘要： A control circuit controls a voltage applied to a memory cell array. A first electrode contacts to a first surface of a variable resistance element, while a second electrode contacts to a second surface of the variable resistance element. The first electrode is configured by a metal, and the second electrode is configured by a P type semiconductor. The control unit, when performing a setting operation of a memory cell, applies a voltage such that a current flows in a direction from the first electrode toward the second electrode.
摘要翻译：控制电路控制施加到存储单元阵列的电压。第一电极接触可变电阻元件的第一表面，而第二电极接触可变电阻元件的第二表面。第一电极由金属构成，第二电极由P型半导体构成。控制单元在进行存储单元的设定动作时，施加电流使得电流从第一电极朝向第二电极的方向流动。

4. 发明申请

US20140061578A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：US20140061578A1
公开(公告)日：2014-03-06
申请号：US13780734
申请日：2013-02-28
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Shigeki KOBAYASHI , Yasuhiro Nojiri , Masaki Yamato , Hiroyuki Fukumizu , Takeshi Yamaguchi
IPC分类号： H01L27/24
CPC分类号： H01L27/2481 , H01L27/2409 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/146
摘要： A nonvolatile semiconductor memory device below comprises: a memory cell array configured having memory cells arranged therein disposed at intersections of a plurality of first lines and a plurality of second lines formed so as to intersect each other, and the memory cells each comprising a variable resistance element; and a control circuit configured to select and drive the first lines and the second lines. The variable resistance element is configured by a transition metal oxide film. The variable resistance element is electrically connected to a first electrode configured from a metal at a first surface and is electrically connected to a second electrode at a second surface which is on an opposite side to the first surface. A first insulating film is formed between the first electrode and the variable resistance element. The first insulating film is formed by a first material that is formed by covalent binding.
摘要翻译：下面的非易失性半导体存储器件包括：存储单元阵列，其配置有存储单元，其布置在多个第一线和形成为彼此交叉的多个第二线的交点处，并且每个存储单元包括可变电阻元件; 以及控制电路，被配置为选择并驱动第一线和第二线。可变电阻元件由过渡金属氧化物膜构成。可变电阻元件电连接到由第一表面上的金属构成的第一电极，并且在与第一表面相反的第二表面处电连接到第二电极。在第一电极和可变电阻元件之间形成第一绝缘膜。第一绝缘膜由通过共价结合形成的第一材料形成。

5. 发明授权

US09634064B2 Semiconductor memory device having stacked word lines and conductive pillar 有权
公开(公告)号：US09634064B2
公开(公告)日：2017-04-25
申请号：US15149494
申请日：2016-05-09
申请人： Kabushiki Kaisha Toshiba
发明人： Masaki Yamato , Takeshi Yamaguchi , Shigeki Kobayashi
IPC分类号： H01L27/24 , H01L45/00
CPC分类号： H01L27/2481 , H01L27/2463 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/1616 , H01L45/1683
摘要： According to one embodiment, a manufacturing method of a semiconductor memory device includes forming a stacked body in which word line material layers and insulating layers are alternately stacked on a base layer. The method includes forming first holes on the stacked body so as to be arranged in a first direction and in a second direction that intersects with the first direction. The method includes forming resistance-change films on inner walls of the first holes, forming bit lines inside the resistance-change films in the first holes, and dividing the stacked body in the first direction by forming second holes so that a portion in the stacked body adjacent to the resistance-change films in the second direction. The method includes forming inter-bit line insulating films in the second holes.

6. 发明授权

US09559300B2 Resistive random access memory device and manufacturing method thereof 有权
标题翻译：电阻随机存取存储器件及其制造方法
公开(公告)号：US09559300B2
公开(公告)日：2017-01-31
申请号：US14472670
申请日：2014-08-29
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Hiroyuki Ode , Takeshi Yamaguchi , Takeshi Takagi , Toshiharu Tanaka , Masaki Yamato
IPC分类号： H01L27/10 , H01L45/00 , G11C13/00 , G11C11/419 , H01L27/118 , H01L27/115 , H01L27/24 , H01L27/112
CPC分类号： H01L45/146 , G11C11/419 , G11C13/0007 , G11C13/0009 , G11C13/004 , G11C13/0069 , G11C2013/005 , G11C2013/0073 , G11C2013/009 , G11C2213/32 , G11C2213/51 , G11C2213/52 , G11C2213/71 , H01L27/11206 , H01L27/115 , H01L27/118 , H01L27/24 , H01L27/2409 , H01L27/249 , H01L45/04 , H01L45/085 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/16
摘要： In accordance with an embodiment, a resistive random access memory device includes a substrate, first and second wiring lines, and a storage cell. The first and second wiring lines are disposed on the substrate so as to intersect each other. The storage cell is disposed between the first and second wiring lines at the intersection of the first and second wiring lines and includes a first electrode, a resistive switching film on the first electrode, a second electrode on the resistive switching film, and a tantalum oxide (TaOx) layer. The first electrode is electrically connected to the first wiring line. The second electrode is electrically connected to the second wiring line. The tantalum oxide (TaOx) layer is disposed between the first electrode and the resistive switching film and is in contact with the resistive switching film.
摘要翻译：根据实施例，电阻随机存取存储器件包括衬底，第一和第二布线以及存储单元。第一和第二布线被布置在基板上以便彼此相交。存储单元设置在第一和第二布线之间的第一和第二布线的交点处，并且包括第一电极，第一电极上的电阻切换膜，电阻开关膜上的第二电极和氧化钽（TaOx）层。第一电极电连接到第一布线。第二电极电连接到第二布线。氧化钽（TaOx）层设置在第一电极和电阻开关膜之间并与电阻开关膜接触。

7. 发明申请

US20160019959A1 NONVOLATILE MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME 有权
标题翻译：非易失性存储器件及其控制方法
公开(公告)号：US20160019959A1
公开(公告)日：2016-01-21
申请号：US14635448
申请日：2015-03-02
申请人： Kabushiki Kaisha Toshiba
发明人： Takeshi TAKAGI , Masaki Yamato , Hiroyuki Ode , Takeshi Yamaguchi , Toshiharu Tanaka
IPC分类号： G11C13/00 , G06F11/07
CPC分类号： G11C13/0069 , G06F11/073 , G06F11/076 , G06F11/0793 , G11C13/0007 , G11C13/0064 , G11C13/0097 , G11C2013/0092 , G11C2213/71
摘要： A nonvolatile memory device comprises a memory cell comprising a variable resistance element connected between a couple of wirings and a control circuit applying a voltage between the couple of wirings connected to the memory cell. In data rewriting, the control circuit repeats a first voltage application step of applying a first write voltage between the couple of wirings and a first verify step of applying a first voltage lower than the first write voltage between the couple of wirings and comparing a cell current through the cell with a first threshold current, the steps repeated until a magnitude relation of the cell current and the first threshold current satisfies a first condition. If the first condition is satisfied, the circuit performs a second voltage application step of applying a second write voltage between the couple of wirings.
摘要翻译：非易失性存储器件包括存储单元，该存储单元包括连接在一对布线之间的可变电阻元件和在连接到存储单元的布线对之间施加电压的控制电路。在数据重写中，控制电路重复第一电压施加步骤，在所述布线对之间施加第一写入电压，以及第一验证步骤，在所述布线对之间施加低于所述第一写入电压的第一电压，并且比较电池电流通过具有第一阈值电流的单元，重复步骤，直到单元电流和第一阈值电流的大小关系满足第一条件。如果满足第一条件，则电路执行施加第二写入电压在两对布线之间的第二电压施加步骤。

8. 发明授权

US09209394B2 Resistance change element and method for manufacturing same 有权
标题翻译：电阻变化元件及其制造方法
公开(公告)号：US09209394B2
公开(公告)日：2015-12-08
申请号：US14188892
申请日：2014-02-25
申请人： Kabushiki Kaisha Toshiba
发明人： Hiroyuki Ode , Takeshi Yamaguchi , Masaki Yamato , Shigeki Kobayashi , Yoshinori Nakakubo
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L45/146 , H01L27/2481 , H01L27/249 , H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/1608
摘要： According to one embodiment, a resistance change element includes: a first electrode; a second electrode; and a resistance change film provided between the first electrode and the second electrode, and the resistance change film including: a first transition metal oxide-containing layer; a second transition metal oxide-containing layer; and an intermediate layer provided between the first transition metal oxide-containing layer and the second transition metal oxide-containing layer, the intermediate layer having a higher crystallization temperature than the first transition metal oxide-containing layer and the second transition metal oxide-containing layer, and the intermediate layer including an amorphous material.
摘要翻译：根据一个实施例，电阻变化元件包括：第一电极; 第二电极; 以及设置在所述第一电极和所述第二电极之间的电阻变化膜，所述电阻变化膜包括：第一过渡金属氧化物含有层; 第二过渡金属氧化物层; 以及设置在所述第一过渡金属氧化物含有层和所述第二过渡金属氧化物含有层之间的中间层，所述中间层的结晶温度高于所述第一过渡金属氧化物含有层和所述第二过渡金属氧化物含有层，中间层包括无定形材料。

9. 发明授权

US08971092B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08971092B2
公开(公告)日：2015-03-03
申请号：US14021052
申请日：2013-09-09
申请人： Kabushiki Kaisha Toshiba
发明人： Shigeki Kobayashi , Yasuhiro Nojiri , Masaki Yamato , Hiroyuki Fukumizu , Takeshi Yamaguchi
IPC分类号： G11C11/00 , G11C13/00 , G11C19/00
CPC分类号： G11C13/0007 , G11C13/0023 , G11C13/0038 , G11C13/0069 , G11C19/00 , G11C2213/71 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146
摘要： A memory cell array includes first wiring lines, and second wiring lines, the first and second wiring lines intersecting, and memory cells disposed in the intersections of the first and second wiring lines, the memory cells including a variable resistance element. A control circuit controls voltages of selected first and second wiring lines. The first wiring lines are arranged at a first pitch in a first direction perpendicular to a substrate and extend in a second direction parallel to the substrate. The second wiring lines are arranged at a second pitch in the second direction and extend in the first direction. The control circuit is configured to change voltages applied to a selected first wiring line according to the positions of the selected first wiring lines in the first direction.
摘要翻译：存储单元阵列包括第一布线，第二布线，第一布线和第二布线相交，以及设置在第一布线和第二布线的交叉点中的存储单元，存储单元包括可变电阻元件。控制电路控制所选择的第一和第二布线的电压。第一布线沿垂直于基板的第一方向以第一间距布置，并且在平行于基板的第二方向上延伸。第二布线沿第二方向以第二间距布置，并沿第一方向延伸。控制电路被配置为根据所选择的第一布线在第一方向上的位置来改变施加到所选择的第一布线的电压。

10. 发明申请

US20140061567A1 NONVOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件
公开(公告)号：US20140061567A1
公开(公告)日：2014-03-06
申请号：US13848318
申请日：2013-03-21
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Shigeki Kobayashi , Takeshi Yamaguchi , Yasuhiro Nojiri , Masaki Yamato , Hiroyuki Fukumizu
IPC分类号： H01L45/00
CPC分类号： H01L45/12 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/147
摘要： According to one embodiment, a nonvolatile memory device includes a first wiring, a second wiring, and a memory cell provided between the first wiring and the second wiring. The memory cell includes a memory layer, a rectifying element layer, and a protective resistance layer including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type.
摘要翻译：根据一个实施例，非易失性存储器件包括第一布线，第二布线和设置在第一布线和第二布线之间的存储单元。存储单元包括存储层，整流元件层和包括第一导电类型的第一半导体层和第二导电类型的第二半导体层的保护电阻层。

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