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1. 发明授权

US09679947B2 Semiconductor memory device 有权
公开(公告)号：US09679947B2
公开(公告)日：2017-06-13
申请号：US15412171
申请日：2017-01-23
申请人： Kabushiki Kaisha Toshiba
发明人： Masaki Yamato , Yasuhiro Nojiri , Shigeki Kobayashi , Hiroyuki Fukumizu , Takeshi Yamaguchi
IPC分类号： H01L27/24 , H01L45/00
CPC分类号： H01L27/249 , H01L27/2454 , H01L27/2472 , H01L45/04 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/146
摘要： A plurality of first conductive layers are stacked at a predetermined pitch in a first direction perpendicular to a substrate. A memory layer is provided in common on side surfaces of the first conductive layers and functions as the memory cells. A second conductive layer comprises a first side surface in contact with side surfaces of the first conductive layers via the memory layer, the second conductive layer extending in the first direction. A width in a second direction of the first side surface at a first position is smaller than a width in the second direction of the first side surface at a second position lower than the first position. A thickness in the first direction of the first conductive layer at the first position is larger than a thickness in the first direction of the first conductive layer at the second position.

2. 发明申请

US20160099289A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20160099289A1
公开(公告)日：2016-04-07
申请号：US14966184
申请日：2015-12-11
申请人： Kabushiki Kaisha Toshiba
发明人： Masaki YAMATO , Yasuhiro Nojiri , Shigeki Kobayashi , Hiroyuki Fukumizu , Takeshi Yamaguchi
IPC分类号： H01L27/24 , H01L45/00
CPC分类号： H01L27/249 , H01L27/2454 , H01L27/2472 , H01L45/04 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/146
摘要： A plurality of first conductive layers are stacked at a predetermined pitch in a first direction perpendicular to a substrate. A memory layer is provided in common on side surfaces of the first conductive layers and functions as the memory cells. A second conductive layer comprises a first side surface in contact with side surfaces of the first conductive layers via the memory layer, the second conductive layer extending in the first direction. A width in a second direction of the first side surface at a first position is smaller than a width in the second direction of the first side surface at a second position lower than the first position. A thickness in the first direction of the first conductive layer at the first position is larger than a thickness in the first direction of the first conductive layer at the second position.
摘要翻译：多个第一导电层以垂直于基板的第一方向以预定间距堆叠。在第一导电层的侧表面上共同提供存储层，并且用作存储单元。第二导电层包括经由存储层与第一导电层的侧表面接触的第一侧表面，第二导电层沿第一方向延伸。在第一位置处的第一侧表面的第二方向上的宽度小于在比第一位置低的第二位置处的第一侧表面的第二方向上的宽度。第一导电层在第一位置的第一方向上的厚度大于第二导电层在第二位置的第一方向上的厚度。

3. 发明授权

US08912521B2 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08912521B2
公开(公告)日：2014-12-16
申请号：US13845935
申请日：2013-03-18
申请人： Kabushiki Kaisha Toshiba
发明人： Yasuhiro Nojiri , Hiroyuki Fukumizu , Shigeki Kobayashi , Masaki Yamato
IPC分类号： H01L29/02 , H01L27/24 , H01L45/00
CPC分类号： H01L45/16 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L45/149
摘要： First conductive layers extend in a first direction horizontal to a substrate as a longitudinal direction, and are stacked in a direction perpendicular to a substrate. An interlayer insulating layer is provided between the first conductive layers. The variable resistance layers functioning as a variable resistance element are formed continuously on the side surfaces of the first conductive layers and the interlayer insulating layer. A columnar conductive layer is provided on the side surfaces of the first conductive layers and the interlayer insulating layer via the variable resistance layers. First side surfaces of the first conductive layers are recessed from a second side surface of the interlayer insulating layer in the direction away from the columnar conductive layers.
摘要翻译：第一导电层沿着与基板垂直的第一方向作为纵向方向延伸，并且在垂直于基板的方向上堆叠。在第一导电层之间设置层间绝缘层。用作可变电阻元件的可变电阻层在第一导电层和层间绝缘层的侧表面上连续地形成。通过可变电阻层，在第一导电层和层间绝缘层的侧表面上设置柱状导电层。第一导电层的第一侧表面从层间绝缘层的第二侧表面沿远离柱状导电层的方向凹陷。

4. 发明申请

US20140241037A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20140241037A1
公开(公告)日：2014-08-28
申请号：US14021052
申请日：2013-09-09
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Shigeki KOBAYASHI , Yasuhiro Nojiri , Masaki Yamato , Hiroyuki Fukumizu , Takeshi Yamaguchi
IPC分类号： G11C13/00
CPC分类号： G11C13/0007 , G11C13/0023 , G11C13/0038 , G11C13/0069 , G11C19/00 , G11C2213/71 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146
摘要： A memory cell array includes first wiring lines, and second wiring lines, the first and second wiring lines intersecting, and memory cells disposed in the intersections of the first and second wiring lines, the memory cells including a variable resistance element. A control circuit controls voltages of selected first and second wiring lines. The first wiring lines are arranged at a first pitch in a first direction perpendicular to a substrate and extend in a second direction parallel to the substrate. The second wiring lines are arranged at a second pitch in the second direction and extend in the first direction. The control circuit is configured to change voltages applied to a selected first wiring line according to the positions of the selected first wiring lines in the first direction.
摘要翻译：存储单元阵列包括第一布线，第二布线，第一布线和第二布线相交，以及设置在第一布线和第二布线的交叉点中的存储单元，存储单元包括可变电阻元件。控制电路控制所选择的第一和第二布线的电压。第一布线沿垂直于基板的第一方向以第一间距布置，并且在平行于基板的第二方向上延伸。第二布线沿第二方向以第二间距布置，并沿第一方向延伸。控制电路被配置为根据所选择的第一布线在第一方向上的位置来改变施加到所选择的第一布线的电压。

5. 发明授权

US09252358B2 Semiconductor memory device and method of manufacturing the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US09252358B2
公开(公告)日：2016-02-02
申请号：US13767029
申请日：2013-02-14
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Hiroshi Kanno , Takayuki Tsukamoto , Hiroyuki Fukumizu , Yoichi Minemura , Takamasa Okawa
IPC分类号： H01L21/332 , H01L29/06 , H01L45/00 , H01L27/24
CPC分类号： H01L45/1206 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L45/16 , H01L45/1658
摘要： First, a trench penetrating first conductive layers and interlayer insulating layers is formed. Next, a column-shaped conductive layer is formed to fill the trench via a side wall layer. Then, after formation of the side wall layer, by migration of oxygen atoms between the side wall layer and the first conductive layers or migration of oxygen atoms between the side wall layer and the interlayer insulating layers, a proportion of oxygen atoms in the side wall layer adjacent to the interlayer insulating layers is made larger than a proportion of oxygen atoms in the side wall layer adjacent to the first conductive layers, whereby the side wall layer adjacent to the first conductive layers is caused to function as the variable resistance element.
摘要翻译：首先，形成穿透第一导电层和层间绝缘层的沟槽。接下来，形成柱状导电层，以通过侧壁层填充沟槽。然后，在形成侧壁层之后，通过在侧壁层和第一导电层之间迁移氧原子或者在侧壁层和层间绝缘层之间迁移氧原子，侧壁中的氧原子的比例使与层间绝缘层相邻的层的厚度大于与第一导电层相邻的侧壁层中的氧原子的比例，由此使与第一导电层相邻的侧壁层起到可变电阻元件的作用。

6. 发明授权

US09246088B2 Semiconductor memory device having a variable resistance layer serving as a memory layer 有权
标题翻译：具有用作存储层的可变电阻层的半导体存储器件
公开(公告)号：US09246088B2
公开(公告)日：2016-01-26
申请号：US14026204
申请日：2013-09-13
申请人： Kabushiki Kaisha Toshiba
发明人： Masaki Yamato , Yasuhiro Nojiri , Shigeki Kobayashi , Hiroyuki Fukumizu , Takeshi Yamaguchi
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L27/249 , H01L27/2454 , H01L27/2472 , H01L45/04 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/146
摘要： A plurality of first conductive layers are stacked at a predetermined pitch in a first direction perpendicular to a substrate. A memory layer is provided in common on side surfaces of the first conductive layers and functions as the memory cells. A second conductive layer comprises a first side surface in contact with side surfaces of the first conductive layers via the memory layer, the second conductive layer extending in the first direction. A width in a second direction of the first side surface at a first position is smaller than a width in the second direction of the first side surface at a second position lower than the first position. A thickness in the first direction of the first conductive layer at the first position is larger than a thickness in the first direction of the first conductive layer at the second position.
摘要翻译：多个第一导电层以垂直于基板的第一方向以预定间距堆叠。在第一导电层的侧表面上共同提供存储层，并且用作存储单元。第二导电层包括经由存储层与第一导电层的侧表面接触的第一侧表面，第二导电层沿第一方向延伸。在第一位置处的第一侧表面的第二方向上的宽度小于在比第一位置低的第二位置处的第一侧表面的第二方向上的宽度。第一导电层在第一位置的第一方向上的厚度大于第二导电层在第二位置的第一方向上的厚度。

7. 发明授权

US09590016B2 3D semiconductor memory device having variable resistance memory elements 有权
标题翻译：具有可变电阻存储元件的3D半导体存储器件
公开(公告)号：US09590016B2
公开(公告)日：2017-03-07
申请号：US14966184
申请日：2015-12-11
申请人： Kabushiki Kaisha Toshiba
发明人： Masaki Yamato , Yasuhiro Nojiri , Shigeki Kobayashi , Hiroyuki Fukumizu , Takeshi Yamaguchi
IPC分类号： H01L27/24 , H01L45/00
CPC分类号： H01L27/249 , H01L27/2454 , H01L27/2472 , H01L45/04 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/146
摘要： A plurality of first conductive layers are stacked at a predetermined pitch in a first direction perpendicular to a substrate. A memory layer is provided in common on side surfaces of the first conductive layers and functions as the memory cells. A second conductive layer comprises a first side surface in contact with side surfaces of the first conductive layers via the memory layer, the second conductive layer extending in the first direction. A width in a second direction of the first side surface at a first position is smaller than a width in the second direction of the first side surface at a second position lower than the first position. A thickness in the first direction of the first conductive layer at the first position is larger than a thickness in the first direction of the first conductive layer at the second position.
摘要翻译：多个第一导电层以垂直于基板的第一方向以预定间距堆叠。在第一导电层的侧表面上共同提供存储层，并且用作存储单元。第二导电层包括经由存储层与第一导电层的侧表面接触的第一侧表面，第二导电层沿第一方向延伸。在第一位置处的第一侧表面的第二方向上的宽度小于在比第一位置低的第二位置处的第一侧表面的第二方向上的宽度。第一导电层在第一位置的第一方向上的厚度大于第二导电层在第二位置的第一方向上的厚度。

8. 发明授权

US09007809B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US09007809B2
公开(公告)日：2015-04-14
申请号：US13778762
申请日：2013-02-27
申请人： Kabushiki Kaisha Toshiba
发明人： Hiroyuki Fukumizu , Shigeki Kobayashi , Yasuhiro Nojiri , Masaki Yamato , Takeshi Yamaguchi
IPC分类号： G11C13/00 , H01L45/00 , H01L27/24
CPC分类号： G11C13/0002 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2013/0083 , G11C2213/52 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/146
摘要： A control circuit controls a voltage applied to a memory cell array. A first electrode contacts to a first surface of a variable resistance element, while a second electrode contacts to a second surface of the variable resistance element. The first electrode is configured by a metal, and the second electrode is configured by a P type semiconductor. The control unit, when performing a setting operation of a memory cell, applies a voltage such that a current flows in a direction from the first electrode toward the second electrode.
摘要翻译：控制电路控制施加到存储单元阵列的电压。第一电极接触可变电阻元件的第一表面，而第二电极接触可变电阻元件的第二表面。第一电极由金属构成，第二电极由P型半导体构成。控制单元在进行存储单元的设定动作时，施加电流使得电流从第一电极朝向第二电极的方向流动。

9. 发明申请

US20140061578A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：US20140061578A1
公开(公告)日：2014-03-06
申请号：US13780734
申请日：2013-02-28
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Shigeki KOBAYASHI , Yasuhiro Nojiri , Masaki Yamato , Hiroyuki Fukumizu , Takeshi Yamaguchi
IPC分类号： H01L27/24
CPC分类号： H01L27/2481 , H01L27/2409 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/146
摘要： A nonvolatile semiconductor memory device below comprises: a memory cell array configured having memory cells arranged therein disposed at intersections of a plurality of first lines and a plurality of second lines formed so as to intersect each other, and the memory cells each comprising a variable resistance element; and a control circuit configured to select and drive the first lines and the second lines. The variable resistance element is configured by a transition metal oxide film. The variable resistance element is electrically connected to a first electrode configured from a metal at a first surface and is electrically connected to a second electrode at a second surface which is on an opposite side to the first surface. A first insulating film is formed between the first electrode and the variable resistance element. The first insulating film is formed by a first material that is formed by covalent binding.
摘要翻译：下面的非易失性半导体存储器件包括：存储单元阵列，其配置有存储单元，其布置在多个第一线和形成为彼此交叉的多个第二线的交点处，并且每个存储单元包括可变电阻元件; 以及控制电路，被配置为选择并驱动第一线和第二线。可变电阻元件由过渡金属氧化物膜构成。可变电阻元件电连接到由第一表面上的金属构成的第一电极，并且在与第一表面相反的第二表面处电连接到第二电极。在第一电极和可变电阻元件之间形成第一绝缘膜。第一绝缘膜由通过共价结合形成的第一材料形成。

10. 发明申请

US20160027682A1 MANUFACTURING METHOD FOR A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：US20160027682A1
公开(公告)日：2016-01-28
申请号：US14636000
申请日：2015-03-02
申请人： Kabushiki Kaisha Toshiba
发明人： Shintaro Okujo , Kenichi Yoshino , Hiroyuki Fukumizu , Satoshi Kato
IPC分类号： H01L21/762 , H01L27/146
CPC分类号： H01L21/76227 , H01L21/763 , H01L27/1463 , H01L27/1464 , H01L27/14683
摘要： According to the embodiments, a manufacturing method for a semiconductor device includes forming recessed parts on a surface of a semiconductor layer. The manufacturing method for the semiconductor device includes a process for forming a buffer layer, which has a melting point lower than that of the semiconductor layer, on a surface of the recessed part on the surface of the semiconductor layer. The manufacturing method for the semiconductor device includes a process for forming a high-melting point film, which has the melting point higher than that of the semiconductor layer, on the buffer layer and fills the recessed part with the high-melting point film. The manufacturing method for the semiconductor device includes a process for heating the semiconductor layer having the buffer layer and the high-melting point film formed thereon at a temperature equal to or higher than the melting point of the buffer layer.
摘要翻译：根据实施例，半导体器件的制造方法包括在半导体层的表面上形成凹部。半导体器件的制造方法包括在半导体层的表面上的凹部的表面上形成熔点低于半导体层的缓冲层的工序。半导体器件的制造方法包括在缓冲层上形成熔点高于半导体层的熔点的高熔点膜的方法，并用高熔点膜填充凹部。半导体器件的制造方法包括在等于或高于缓冲层的熔点的温度下加热具有缓冲层的半导体层和形成在其上的高熔点膜的工艺。

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