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1. 发明授权

US6144052A Semiconductor device and its manufacture 有权
标题翻译：半导体器件及其制造
公开(公告)号：US6144052A
公开(公告)日：2000-11-07
申请号：US142011
申请日：1998-08-31
申请人： Keiko Kushida , Masahiko Hiratani , Kazuyoshi Torii , Shinichiro Takatani , Hiroshi Miki , Yuuichi Matsui , Yoshihisa Fujisaki
发明人： Keiko Kushida , Masahiko Hiratani , Kazuyoshi Torii , Shinichiro Takatani , Hiroshi Miki , Yuuichi Matsui , Yoshihisa Fujisaki
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L29/72
CPC分类号： H01L27/10852 , H01L28/55 , H01L28/60 , H01L27/10814 , H01L27/10888
摘要： An oriented polycrystal silicon film or an amorphous silicon film 52 is disposed on the whole area beneath a conductive diffusion barrier 61 under a lower electrode of a ferroelectric capacitor. As a result, the conductive diffusion barrier, the lower electrode and the capacitor ferroelectric film become oriented films; therefore, it is possible to reduce the signal variation in capacitors even in minute semiconductor devices, and obtain a highly reliable semiconductor device.
摘要翻译： PCT No.PCT / JP96 / 00579 Sec。 371日期1998年8月31日 102（e）1998年8月31日PCT 1996年3月8日PCT公布。公开号WO97 / 33316 PCT 日期1997年9月12日在铁电电容器的下电极下方的导电性扩散阻挡层61的下方的整个区域上设置取向多晶硅膜或非晶硅膜52。结果，导电扩散阻挡层，下电极和电容器铁电体膜成为取向膜; 因此，即使在微小的半导体器件中也可以减小电容器的信号变化，并获得高可靠性的半导体器件。

2. 发明授权

US5914068A Bi-layer oxide ferroelectrics 失效
标题翻译：双层氧化物铁电体
公开(公告)号：US5914068A
公开(公告)日：1999-06-22
申请号：US765575
申请日：1996-12-30
申请人： Masahiko Hiratani , Keiko Kushida , Kazushige Imagawa , Kazumasa Takagi
发明人： Masahiko Hiratani , Keiko Kushida , Kazushige Imagawa , Kazumasa Takagi
IPC分类号： C04B35/453 , C30B29/22
CPC分类号： C04B35/453
摘要： Novel Bi-layer Perovskite ferroelectrics constituted of BiO intermediate layers (17) and pseudo-Perovskite layers (18) stacked alternately are disclosed. The Bi-layer Perovskite ferroelectrics have such a crystal structure which has a fundamental skeleton composed of each intermediate layer (17) consisting of one BiO plane and each pseudo-Perovskite structure (18) consisting of Pb(Zr, Ti)O.sub.3. Since the intermediate layer (17) is constituted of the BiO layer, the ferroelectrics are more excellent in ferroelectric characteristics and thermodynamic stability than known Perovskite ferroelectrics comprising a Bi.sub.2 O.sub.2 layer.
摘要翻译： PCT No.PCT / JP95 / 01205 Sec。 371日期1996年12月30日第 102（e）日期1996年12月30日PCT归档1995年6月16日PCT公布。出版物WO96 / 00704 日期1996年1月11日公开了由交替堆叠的BiO中间层（17）和伪钙钛矿层（18）构成的新型双层钙钛矿型铁电体。双层钙钛矿铁电体具有这样的晶体结构，其具有由由一个BiO平面构成的每个中间层（17）和由Pb（Zr，Ti）O 3组成的每个假钙钛矿结构（18）组成的基本骨架。由于中间层（17）由BiO层构成，所以铁电体的铁电特性和热力学稳定性优于包括Bi 2 O 2层的已知钙钛矿型铁电体。

3. 发明授权

US06787451B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06787451B2
公开(公告)日：2004-09-07
申请号：US10216792
申请日：2002-08-13
申请人： Yasuhiro Shimamoto , Katsunori Obata , Kazuyoshi Torii , Masahiko Hiratani
发明人： Yasuhiro Shimamoto , Katsunori Obata , Kazuyoshi Torii , Masahiko Hiratani
IPC分类号： H01L2972
CPC分类号： H01L29/4983 , H01L21/0214 , H01L21/02164 , H01L21/02178 , H01L21/02266 , H01L21/02323 , H01L21/02329 , H01L21/02337 , H01L21/28061 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/3141 , H01L21/3143 , H01L21/31612 , H01L21/3162 , H01L21/31641 , H01L21/31645 , H01L28/56 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66545
摘要： In a method for manufacturing an FET having a gate insulation film with an SiO2 equivalent thickness of 2 nm or more and capable of suppressing the leak current to {fraction (1/100)} or less compared with existent SiO2 films, an SiO2 film of 0.5 nm or more is formed at a boundary between an Si substrate (polycrystalline silicon gate) and a high dielectric insulation film, and the temperature for forming the SiO2 film is made higher than the source-drain activating heat treatment temperature in the subsequent steps. As such, a shifting threshold voltage by the generation of static charges or lowering of a drain current caused by degradation of mobility can be prevented so as to reduce electric power consumption and increase current in a field effect transistor of a smaller size.
摘要翻译：在具有SiO 2当量厚度为2nm以上的栅极绝缘膜的FET的制造方法中，能够将漏电流抑制到{部分（与现有的SiO 2膜相比为1/100以下）的SiO 2膜为0.5nm 以上的Si基板（多晶硅栅极）和高介电绝缘膜之间的边界处形成，并且使SiO 2膜的形成温度高于后续工序中的源极 - 漏极活化热处理温度，因此可以防止由静电电荷的产生产生的偏移阈值电压或由迁移率降低引起的漏极电流的降低，从而降低较小尺寸的场效应晶体管的电力消耗和增加电流。

4. 发明授权

US07119407B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07119407B2
公开(公告)日：2006-10-10
申请号：US10900430
申请日：2004-07-28
申请人： Yasuhiro Shimamoto , Katsunori Obata , Kazuyoshi Torii , Masahiko Hiratani
发明人： Yasuhiro Shimamoto , Katsunori Obata , Kazuyoshi Torii , Masahiko Hiratani
IPC分类号： H01L29/72
CPC分类号： H01L29/4983 , H01L21/0214 , H01L21/02164 , H01L21/02178 , H01L21/02266 , H01L21/02323 , H01L21/02329 , H01L21/02337 , H01L21/28061 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/3141 , H01L21/3143 , H01L21/31612 , H01L21/3162 , H01L21/31641 , H01L21/31645 , H01L28/56 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66545
摘要： In a method for manufacturing an FET having a gate insulation film with an SiO2 equivalent thickness of 2 nm or more and capable of suppressing the leak current to 1/100 or less compared with existent SiO2 films, an SiO2 film of 0.5 nm or more is formed at a boundary between an Si substrate (polycrystalline silicon gate) and a high dielectric insulation film, and the temperature for forming the SiO2 film is made higher than the source-drain activating heat treatment temperature in the subsequent steps. As such, a shifting threshold voltage by the generation of static charges or lowering of a drain current caused by degradation of mobility can be prevented so as to reduce electric power consumption and increase current in a field effect transistor of a smaller size.
摘要翻译：在具有SiO 2等效厚度为2nm以上的栅极绝缘膜的FET的制造方法中，与现有的SiO 2相比，能够将漏电流抑制到1/100以下，在Si衬底（多晶硅栅极）和高介电绝缘膜之间的边界处形成0.5nm或更大的SiO 2 SiO 2膜，并且形成 SiO 2膜比后续步骤中的源极 - 漏极活化热处理温度高。因此，可以防止由静电电荷的产生产生的偏移阈值电压或由迁移率降低导致的漏极电流的降低，从而降低较小尺寸的场效应晶体管的电力消耗和增加电流。

5. 发明申请

US20070001244A1 Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070001244A1
公开(公告)日：2007-01-04
申请号：US11516629
申请日：2006-09-07
申请人： Yasuhiro Shimamoto , Katsunori Obata , Kazuyoshi Torii , Masahiko Hiratani
发明人： Yasuhiro Shimamoto , Katsunori Obata , Kazuyoshi Torii , Masahiko Hiratani
IPC分类号： H01L29/94
CPC分类号： H01L29/4983 , H01L21/0214 , H01L21/02164 , H01L21/02178 , H01L21/02266 , H01L21/02323 , H01L21/02329 , H01L21/02337 , H01L21/28061 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/3141 , H01L21/3143 , H01L21/31612 , H01L21/3162 , H01L21/31641 , H01L21/31645 , H01L28/56 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66545
摘要： In a method for manufacturing an FET having a gate insulation film with an SiO2 equivalent thickness of 2 nm or more and capable of suppressing the leak current to 1/100 or less compared with existent SiO2 films, an SiO2 film of 0.5 nm or more is formed at a boundary between an Si substrate (polycrystalline silicon gate) and a high dielectric insulation film, and the temperature for forming the SiO2 film is made higher than the source-drain activating heat treatment temperature in the subsequent steps. As such, a shifting threshold voltage by the generation of static charges or lowering of a drain current caused by degradation of mobility can be prevented so as to reduce electric power consumption and increase current in a field effect transistor of a smaller size.
摘要翻译：在具有SiO 2等效厚度为2nm以上的栅极绝缘膜的FET的制造方法中，与现有的SiO 2相比，能够将漏电流抑制到1/100以下，在Si衬底（多晶硅栅极）和高介电绝缘膜之间的边界处形成0.5nm或更大的SiO 2 SiO 2膜，并且形成 SiO 2膜比后续步骤中的源极 - 漏极活化热处理温度高。因此，可以防止由静电电荷的产生产生的偏移阈值电压或由迁移率降低导致的漏极电流的降低，从而降低较小尺寸的场效应晶体管的电力消耗和增加电流。

6. 发明授权

US06509246B2 Production of semiconductor integrated circuit 失效
公开(公告)号：US06509246B2
公开(公告)日：2003-01-21
申请号：US09877207
申请日：2001-06-11
申请人： Hiroshi Miki , Yasuhiro Shimamoto , Masahiko Hiratani , Tomoyuki Hamada
发明人： Hiroshi Miki , Yasuhiro Shimamoto , Masahiko Hiratani , Tomoyuki Hamada
IPC分类号： H01L2120
CPC分类号： H01L28/84 , H01L27/10814 , H01L28/91
摘要： A semiconductor integrated circuit in which the storage capacitor has an increased capacitance and a decreased leakage current. The storage capacitor is formed by the steps of: forming a polysilicon bottom electrode having semispherical silicon crystals formed thereon; performing plasma nitriding on the surface of said bottom electrode at a temperature lower than 550° C., thereby forming a film of silicon nitride having a film thickness smaller than 1.5 nm; and depositing a film of amorphous tantalum pentoxide and then crystallizing said amorphous tantalum pentoxide. The silicon nitride film has improved resistance to oxidation and also has a reduced leakage current. As a result, the polysilicon bottom electrode becomes resistant to oxidation and the storage capacitor increases in capacitance and decreases in leakage current.

7. 发明授权

US06583023B2 Method for making semiconductor integrated circuits 有权
标题翻译：制造半导体集成电路的方法
公开(公告)号：US06583023B2
公开(公告)日：2003-06-24
申请号：US10118887
申请日：2002-04-10
申请人： Yasuhiro Shimamoto , Hiroshi Miki , Masahiko Hiratani
发明人： Yasuhiro Shimamoto , Hiroshi Miki , Masahiko Hiratani
IPC分类号： H01L2120
CPC分类号： H01L28/40 , H01L21/31604 , H01L27/10814 , H01L28/56 , H01L28/84 , H01L28/90
摘要： A capacitor having an equivalent thickness of 3.0 nm or less, with a sufficient static capacitance and less leakage current in a reduced size, constituted by stacking an interfacial film 21 having a physical thickness of 2.5 nm or more for suppressing tunnel leakage current and a high dielectric film 22 comprising tantalum pentaoxide on lower electrode 19, 20 comprising rugged polycrystal silicon film, the interfacial film 21 comprising a nitride film formed by an LPCVD method, for example, from Al2O3, a mixed phase of Al2O3 and SiO2, ZrSiO4, HfSiO4, a mixed phase of Y2O3 and SiO2, and a mixed phase of La2O3 and SiO2.
摘要翻译：具有3.0nm以下的等效厚度的电容器，具有足够的静电容量和较小的漏电流，通过堆叠具有2.5nm或更大的物理厚度的界面膜21来构成，用于抑制隧道漏电流和高介电膜22包括在下电极19上的五氧化钽，20，包括粗糙多晶硅膜，界面膜21包括通过LPCVD法形成的氮化物膜，例如Al2O3，Al2O3和SiO2的混合相，ZrSiO4，HfSiO4， Y2O3和SiO2的混合相以及La2O3和SiO2的混合相。

8. 发明授权

US06740901B2 Production of semiconductor integrated circuit 失效
标题翻译：生产半导体集成电路
公开(公告)号：US06740901B2
公开(公告)日：2004-05-25
申请号：US10307354
申请日：2002-12-02
申请人： Hiroshi Miki , Yasuhiro Shimamoto , Masahiko Hiratani , Tomoyuki Hamada
发明人： Hiroshi Miki , Yasuhiro Shimamoto , Masahiko Hiratani , Tomoyuki Hamada
IPC分类号： H01L27108
CPC分类号： H01L28/84 , H01L27/10814 , H01L28/91
摘要： A semiconductor integrated circuit in which the storage capacitor has an increased capacitance and a decreased leakage current. The storage capacitor is formed by the steps of: forming a polysilicon bottom electrode having semispherical silicon crystals formed thereon; performing plasma nitriding on the surface of said bottom electrode at a temperature lower than 550° C., thereby forming a film of silicon nitride having a film thickness smaller than 1.5 nm; and depositing a film of amorphous tantalum pentoxide and then crystallizing said amorphous tantalum pentoxide. The silicon nitride film has improved resistance to oxidation and also has a reduced leakage current. As a result, the polysilicon bottom electrode becomes resistant to oxidation and the storage capacitor increases in capacitance and decreases in leakage current.
摘要翻译：一种半导体集成电路，其中存储电容器具有增加的电容和减小的漏电流。存储电容器通过以下步骤形成：形成其上形成有半球形硅晶体的多晶硅底电极; 在低于550℃的温度下在所述底部电极的表面上进行等离子体氮化，从而形成膜厚度小于1.5nm的氮化硅膜; 并沉积无定形钽五氧化物膜，然后使所述无定形五氧化钽结晶。氮化硅膜具有改善的抗氧化性，并且还具有减小的漏电流。结果，多晶硅底部电极变得耐氧化，并且存储电容器增加电容并且减小漏电流。

9. 发明授权

US06693792B2 Semiconductor integrated circuits and fabricating method thereof 失效
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US06693792B2
公开(公告)日：2004-02-17
申请号：US10411282
申请日：2003-04-11
申请人： Yasuhiro Shimamoto , Hiroshi Miki , Masahiko Hiratani
发明人： Yasuhiro Shimamoto , Hiroshi Miki , Masahiko Hiratani
IPC分类号： H01G406
CPC分类号： H01L28/40 , H01L21/31604 , H01L27/10814 , H01L28/56 , H01L28/84 , H01L28/90
摘要： A capacitor having an equivalent thickness of 3.0 nm or less, with a sufficient static capacitance and less leakage current in a reduced size, constituted by stacking an interfacial film 21 having a physical thickness of 2.5 nm or more for suppressing tunnel leakage current and a high dielectric film 22 comprising tantalum pentaoxide on lower electrode 19, 20 comprising rugged polycrystal silicon film, the interfacial film 21 comprising a nitride film formed by an LPCVD method, for example, from Al2O3, a mixed phase of Al2O3 and SiO2, ZrSiO4, HfSiO4, a mixed phase of Y2O3 and SiO2, and a mixed phase of La2O3 and SiO2.
摘要翻译：具有3.0nm以下的等效厚度的电容器，具有足够的静电容量和较小的漏电流，通过堆叠具有2.5nm或更大的物理厚度的界面膜21来构成，用于抑制隧道漏电流和高介电膜22包括在下电极19上的五氧化钽，20，包括粗糙多晶硅膜，界面膜21包括通过LPCVD法形成的氮化物膜，例如Al2O3，Al2O3和SiO2的混合相，ZrSiO4，HfSiO4， Y2O3和SiO2的混合相以及La2O3和SiO2的混合相。

10. 发明授权

US06833577B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06833577B2
公开(公告)日：2004-12-21
申请号：US10300763
申请日：2002-11-21
申请人： Yuichi Matsui , Masahiko Hiratani
发明人： Yuichi Matsui , Masahiko Hiratani
IPC分类号： H01L27108
CPC分类号： H01L21/022 , C23C16/18 , C23C16/405 , C23C16/56 , H01L21/02175 , H01L21/02183 , H01L21/02194 , H01L21/02271 , H01L21/02356 , H01L21/31604 , H01L21/31637 , H01L27/10814 , H01L27/10852 , H01L27/10882 , H01L27/10894 , H01L28/40 , H01L28/56 , H01L28/75 , H01L28/90
摘要： The present invention relates to a structure of a capacitor, in particular using niobium pentoxide, of a semiconductor capacitor memory device. Since niobium pentoxide has a low crystallization temperature of 600° C. or less, niobium pentoxide can suppress the oxidation of a bottom electrode and a barrier metal by heat treatment. However, according to heat treatment at low temperature, carbon incorporated from CVD sources into the film is not easily oxidized or removed. Therefore, a problem that leakage current increases arises. As an insulator film of a capacitor, a layered film composed of a niobium pentoxide film and a tantalum pentoxide film, or a layered film composed of niobium pentoxide films is used. By the use of the niobium pentoxide film, the dielectric constant of the capacitor can be made high and the crystallization temperature can be made low. By multiple-stage formation of the dielectric film, leakage current can be decreased.
摘要翻译：本发明涉及半导体电容器存储器件的电容器的结构，特别是五氧化二铌。由于五氧化二铌具有600℃以下的低结晶温度，所以五氧化二铌可以通过热处理抑制底部电极和阻挡金属的氧化。然而，根据低温热处理，从CVD源引入到膜中的碳不易氧化或除去。因此，出现漏电流增加的问题。作为电容器的绝缘膜，使用由五氧化二铌膜和五氧化二钽膜构成的层叠膜或由五氧化二铌膜构成的层叠膜。通过使用五氧化二铌膜，可以使电容器的介电常数高，可以降低结晶温度。通过电介质膜的多级形成，可以降低泄漏电流。

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