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1. 发明申请

US20110022646A1 PROCESSOR, CONTROL METHOD OF PROCESSOR, AND COMPUTER READABLE STORAGE MEDIUM STORING PROCESSING PROGRAM 有权
标题翻译：处理器，处理器的控制方法和计算机可读存储介质存储处理程序
公开(公告)号：US20110022646A1
公开(公告)日：2011-01-27
申请号：US12836061
申请日：2010-07-14
申请人： Kenichi Kitamura , Shiro Kamoshida
发明人： Kenichi Kitamura , Shiro Kamoshida
IPC分类号： G06F7/44 , G06F5/01
CPC分类号： G06F7/535
摘要： A processor for dividing by calculating repeatedly an n-bit width partial quotient includes, a dividend zero count value counter that counts a dividend zero count value, a divisor zero count value counter that counts a divisor zero count value, a correction value calculator that calculates a correction value to a loop count value, a correction loop count value calculator that calculates a correction loop count value, a dividend shift unit that shifts leftward an absolute value of the dividend by the dividend zero count value and shifts rightward the leftward-shifted absolute value of the dividend by the correction value, a divisor shift unit that shifts leftward an absolute value of the divisor by the divisor zero count value, and a division loop operation unit that divides based on an output value from the dividend shift unit, an output value from the divisor shift unit, and the correction loop count value.
摘要翻译：用于通过重复计算n位宽度部分商进行除法的处理器包括计数除数零计数值的除数零计数值计数器，对除数零计数值进行计数的除数零计数值计数器，计算除数零计数值的校正值计算器循环计数值的校正值，计算校正循环计数值的校正循环计数值计算器，向左移动除数的绝对值乘以除数零计数值并向左移动左移绝对值的除数移位单位除数值除以校正值，除数移位单位，其将除数的绝对值除以除数零计数值的除数移位单位，以及除法运算单元，其根据来自分红移位单位的输出值进行分割，输出来自除数移位单元的值，以及校正循环计数值。

2. 发明授权

US09009209B2 Processor, control method of processor, and computer readable storage medium storing processing program for division operation 有权
标题翻译：处理器，处理器的控制方法和存储用于分割操作的处理程序的计算机可读存储介质
公开(公告)号：US09009209B2
公开(公告)日：2015-04-14
申请号：US12836061
申请日：2010-07-14
申请人： Kenichi Kitamura , Shiro Kamoshida
发明人： Kenichi Kitamura , Shiro Kamoshida
IPC分类号： G06F7/52 , G06F7/535 , G06F7/44
CPC分类号： G06F7/535
摘要： A processor for dividing by calculating repeatedly an n-bit width partial quotient includes, a dividend zero count value counter that counts a dividend zero count value, a divisor zero count value counter that counts a divisor zero count value, a correction value calculator that calculates a correction value to a loop count value, a correction loop count value calculator that calculates a correction loop count value, a dividend shift unit that shifts leftward an absolute value of the dividend by the dividend zero count value and shifts rightward the leftward-shifted absolute value of the dividend by the correction value, a divisor shift unit that shifts leftward an absolute value of the divisor by the divisor zero count value, and a division loop operation unit that divides based on an output value from the dividend shift unit, an output value from the divisor shift unit, and the correction loop count value.
摘要翻译：用于通过重复计算n位宽度部分商进行除法的处理器包括计数除数零计数值的除数零计数值计数器，对除数零计数值进行计数的除数零计数值计数器，计算除数零计数值的校正值计算器循环计数值的校正值，计算校正循环计数值的校正循环计数值计算器，向左移动除数的绝对值乘以除数零计数值并向左移动左移绝对值的除数移位单位除数值除以校正值，除数移位单位，其将除数的绝对值除以除数零计数值的除数移位单位，以及除法运算单元，其根据来自分红移位单位的输出值进行分割，输出来自除数移位单元的值，以及校正循环计数值。

3. 发明授权

US08166092B2 Arithmetic device for performing division or square root operation of floating point number and arithmetic method therefor 失效
标题翻译：用于执行浮点数的除法或平方根操作的算术装置及其算术方法
公开(公告)号：US08166092B2
公开(公告)日：2012-04-24
申请号：US12124696
申请日：2008-05-21
申请人： Shiro Kamoshida
发明人： Shiro Kamoshida
IPC分类号： G06F7/487
CPC分类号： G06F7/4873 , G06F7/49936 , G06F7/5525
摘要： When division X/Y of floating point numbers is performed, bit string data of a mantissa x including a fraction xf of X or a mantissa y including a fraction yf of Y is shifted in accordance with magnitude relation between them to perform a fraction computation. Thereby, a fraction division result in which the position of the most significant bit is fixed at a prescribed digit is generated. When a square root operation √Y is performed, a fraction square root operation result in which the position of the most significant bit is fixed at a prescribed digit is generated by an exception handling if all of the three conditions that all the bits in the fraction of Y are one, a difference between the exponent ye of Y and a bias value b is an odd number, and a rounding mode is a positive infinity direction are satisfied.
摘要翻译：当执行浮点数的分割X / Y时，包括X的分数xf的尾数x的位串数据或包含Y的分数yf的尾数y的位串数据根据它们之间的大小关系而移位，以执行分数计算。因此，产生将最高有效位的位置固定在规定数字的分数除法结果。当执行平方根操作√Y时，通过异常处理产生最高有效位的位置固定在规定数字的小数平方根操作结果，如果所有分数中的所有位都满足三个条件的Y为1，Y的指数y和偏置值b之间的差为奇数，舍入方式为正无穷大方向。

4. 发明授权

US08775899B2 Error correction device, error correction method, and processor 失效
标题翻译：纠错装置，纠错方法和处理器
公开(公告)号：US08775899B2
公开(公告)日：2014-07-08
申请号：US13566285
申请日：2012-08-03
申请人： Shiro Kamoshida
发明人： Shiro Kamoshida
IPC分类号： H03M13/00 , H03M13/11 , H03M13/09 , H03M13/29
CPC分类号： H03M13/11 , H03M13/09 , H03M13/19 , H03M13/2906 , H03M13/2927 , H03M13/2948
摘要： An error correction device includes: an error correction code generator that generates, from information unit data of data with a parity bit which includes m bytes of information unit data in which each byte has n bits of data and a total of m parity bits where 1 bit is provided for every 1 byte of the information unit data, a bit other than a bit corresponding to the parity bit out of bits constituting an error correction code used for correcting an error in the information unit data; an error detector that detects an error in the information unit data by generating an exclusive-OR of the data with a parity bit; and an error corrector that corrects an error in the information unit data by using a parity bit included in the data with a parity bit and the bit generated by the error correction code generator.
摘要翻译：误差校正装置包括：纠错码发生器，其从包含m字节的信息单元数据的奇偶校验位的数据的信息单元数据生成，其中每个字节具有n位数据，以及总共m个奇偶校验位，其中1 为信息单元数据的每1个字节提供位，除了与构成用于校正信息单元数据中的错误的纠错码的位之外的奇偶校验位相对应的位之外的位; 错误检测器，通过产生数据与奇偶校验位的异或来检测信息单元数据中的错误; 以及错误校正器，其通过使用包括在具有奇偶校验位的数据中的奇偶校验位和由纠错码发生器产生的位来校正信息单元数据中的错误。

5. 发明申请

US20100332957A1 Arithmetic circuit, arithmetic processing device, and arithmetic processing method 失效
标题翻译：算术电路，算术处理装置和算术处理方法
公开(公告)号：US20100332957A1
公开(公告)日：2010-12-30
申请号：US12801695
申请日：2010-06-21
申请人： Shiro Kamoshida
发明人： Shiro Kamoshida
IPC分类号： G06F11/07 , G06F7/02
CPC分类号： G06F7/535
摘要： In an arithmetic circuit, every time a numerical value is stored in a register, a partial solution is predicted on the basis of the numerical value, an intermediate value is generated by a predetermined calculation using one or more predicted partial solutions, an extended sign bit is appended to the intermediate value by sign extension, and the intermediate value to which the extended sign bit is appended is stored in the register. In addition, the solution is generated on the basis of the one or more partial solutions. A value of a sign bit constituting the intermediate value stored in the register is compared with a value of the extended sign bit stored in the register, and an error signal is outputted when the value of the sign bit is different from the value of the extended sign bit.
摘要翻译：在运算电路中，每当将数值存储在寄存器中时，基于数值来预测部分解，通过使用一个或多个预测的部分解的预定计算产生中间值，扩展符号位通过符号扩展附加到中间值，并且扩展符号位所附加的中间值存储在寄存器中。此外，该解决方案是基于一个或多个部分解决方案产生的。将构成存储在寄存器中的中间值的符号位的值与存储在寄存器中的扩展符号位的值进行比较，并且当符号位的值与扩展的值不同时，输出错误信号符号位

6. 发明授权

US08539302B2 Error detecting/correcting code generating circuit and method of controlling the same 有权
标题翻译：错误检测/纠错码产生电路及其控制方法
公开(公告)号：US08539302B2
公开(公告)日：2013-09-17
申请号：US12948816
申请日：2010-11-18
申请人： Shiro Kamoshida
发明人： Shiro Kamoshida
IPC分类号： H03M13/00
CPC分类号： H03M13/19 , H03M13/033 , H03M13/618 , H03M13/6575
摘要： An error detecting/correcting code generating circuit includes a first exclusive OR operation circuit that generates log2(n+1) bits of one portion of a redundant portion of error detecting/correcting-code-attached data by rounding up the numbers to the right of the decimal point of log2(n+1) in response to the input of m bytes of an information portion included in error-detection-bit-attached data. The error-detection-bit-attached data includes a redundant portion of m bits of error detection bits allocated to the m bytes of the information portion, the byte having n bits. The circuit also includes a second exclusive OR operation circuit that generates m bits of another portion of the redundant portion of the error detecting/correcting-code-attached data in response to the input of the one portion and the error detection bits.
摘要翻译：错误检测/校正码产生电路包括第一异或运算电路，该第一异或运算电路通过舍入右边的数字来生成错误检测/校正码附加数据的冗余部分的一部分的log2（n + 1）位响应于错误检测位附加数据中包括的信息部分的m字节的输入，log2（n + 1）的小数点。错误检测位附加数据包括分配给信息部分的m个字节的错误检测位的m位的冗余部分，该字节具有n位。电路还包括响应于一部分的输入和错误检测位而产生错误检测/校正码附加数据的冗余部分的另一部分的m位的第二异或运算电路。

7. 发明授权

US08312361B2 Arithmetic circuit, arithmetic processing device, and arithmetic processing method 失效
标题翻译：算术电路，算术处理装置和算术处理方法
公开(公告)号：US08312361B2
公开(公告)日：2012-11-13
申请号：US12801695
申请日：2010-06-21
申请人： Shiro Kamoshida
发明人： Shiro Kamoshida
IPC分类号： H03M13/00
CPC分类号： G06F7/535
摘要： In an arithmetic circuit, every time a numerical value is stored in a register, a partial solution is predicted on the basis of the numerical value, an intermediate value is generated by a predetermined calculation using one or more predicted partial solutions, an extended sign bit is appended to the intermediate value by sign extension, and the intermediate value to which the extended sign bit is appended is stored in the register. In addition, the solution is generated on the basis of the one or more partial solutions. A value of a sign bit constituting the intermediate value stored in the register is compared with a value of the extended sign bit stored in the register, and an error signal is outputted when the value of the sign bit is different from the value of the extended sign bit.
摘要翻译：在运算电路中，每当将数值存储在寄存器中时，基于数值来预测部分解，通过使用一个或多个预测的部分解的预定计算产生中间值，扩展符号位通过符号扩展附加到中间值，并且扩展符号位所附加的中间值存储在寄存器中。此外，该解决方案是基于一个或多个部分解决方案产生的。将构成存储在寄存器中的中间值的符号位的值与存储在寄存器中的扩展符号位的值进行比较，并且当符号位的值与扩展的值不同时，输出错误信号符号位

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